alu.tan.qmsg

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

{ "Info" "ITDB_TSU_RESULT" "result_t\[12\] OP\[0\] clk 12.762 ns register " "Info: tsu for register \"result_t\[12\]\" (data pin = \"OP\[0\]\", clock pin = \"clk\") is 12.762 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.679 ns + Longest pin register " "Info: + Longest pin to register delay is 15.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns OP\[0\] 1 PIN PIN_12 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_12; Fanout = 51; PIN Node = 'OP\[0\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { OP[0] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.714 ns) + CELL(0.590 ns) 8.773 ns result_t\[2\]~775 2 COMB LC_X11_Y15_N8 7 " "Info: 2: + IC(6.714 ns) + CELL(0.590 ns) = 8.773 ns; Loc. = LC_X11_Y15_N8; Fanout = 7; COMB Node = 'result_t\[2\]~775'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "7.304 ns" { OP[0] result_t[2]~775 } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.292 ns) 10.684 ns Mux~3139 3 COMB LC_X9_Y12_N6 1 " "Info: 3: + IC(1.619 ns) + CELL(0.292 ns) = 10.684 ns; Loc. = LC_X9_Y12_N6; Fanout = 1; COMB Node = 'Mux~3139'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.911 ns" { result_t[2]~775 Mux~3139 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.567 ns) + CELL(0.590 ns) 12.841 ns Mux~3141 4 COMB LC_X10_Y13_N1 1 " "Info: 4: + IC(1.567 ns) + CELL(0.590 ns) = 12.841 ns; Loc. = LC_X10_Y13_N1; Fanout = 1; COMB Node = 'Mux~3141'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.157 ns" { Mux~3139 Mux~3141 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 13.137 ns Mux~3142 5 COMB LC_X10_Y13_N2 1 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 13.137 ns; Loc. = LC_X10_Y13_N2; Fanout = 1; COMB Node = 'Mux~3142'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.296 ns" { Mux~3141 Mux~3142 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 13.867 ns Mux~3143 6 COMB LC_X10_Y13_N7 1 " "Info: 6: + IC(0.438 ns) + CELL(0.292 ns) = 13.867 ns; Loc. = LC_X10_Y13_N7; Fanout = 1; COMB Node = 'Mux~3143'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.730 ns" { Mux~3142 Mux~3143 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.205 ns) + CELL(0.607 ns) 15.679 ns result_t\[12\] 7 REG LC_X9_Y14_N9 2 " "Info: 7: + IC(1.205 ns) + CELL(0.607 ns) = 15.679 ns; Loc. = LC_X9_Y14_N9; Fanout = 2; REG Node = 'result_t\[12\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.812 ns" { Mux~3143 result_t[12] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.954 ns 25.22 % " "Info: Total cell delay = 3.954 ns ( 25.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.725 ns 74.78 % " "Info: Total interconnect delay = 11.725 ns ( 74.78 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "15.679 ns" { OP[0] result_t[2]~775 Mux~3139 Mux~3141 Mux~3142 Mux~3143 result_t[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.679 ns" { OP[0] OP[0]~out0 result_t[2]~775 Mux~3139 Mux~3141 Mux~3142 Mux~3143 result_t[12] } { 0.000ns 0.000ns 6.714ns 1.619ns 1.567ns 0.182ns 0.438ns 1.205ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.590ns 0.114ns 0.292ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 53; CLK Node = 'clk'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { clk } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns result_t\[12\] 2 REG LC_X9_Y14_N9 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X9_Y14_N9; Fanout = 2; REG Node = 'result_t\[12\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.485 ns" { clk result_t[12] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[12] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "15.679 ns" { OP[0] result_t[2]~775 Mux~3139 Mux~3141 Mux~3142 Mux~3143 result_t[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.679 ns" { OP[0] OP[0]~out0 result_t[2]~775 Mux~3139 Mux~3141 Mux~3142 Mux~3143 result_t[12] } { 0.000ns 0.000ns 6.714ns 1.619ns 1.567ns 0.182ns 0.438ns 1.205ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.590ns 0.114ns 0.292ns 0.607ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[12] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk result\[11\] result_t\[11\] 8.731 ns register " "Info: tco from clock \"clk\" to destination pin \"result\[11\]\" through register \"result_t\[11\]\" is 8.731 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 53; CLK Node = 'clk'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { clk } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns result_t\[11\] 2 REG LC_X7_Y13_N3 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y13_N3; Fanout = 2; REG Node = 'result_t\[11\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.485 ns" { clk result_t[11] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.553 ns + Longest register pin " "Info: + Longest register to pin delay is 5.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns result_t\[11\] 1 REG LC_X7_Y13_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N3; Fanout = 2; REG Node = 'result_t\[11\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { result_t[11] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.429 ns) + CELL(2.124 ns) 5.553 ns result\[11\] 2 PIN PIN_60 0 " "Info: 2: + IC(3.429 ns) + CELL(2.124 ns) = 5.553 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'result\[11\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "5.553 ns" { result_t[11] result[11] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 38.25 % " "Info: Total cell delay = 2.124 ns ( 38.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.429 ns 61.75 % " "Info: Total interconnect delay = 3.429 ns ( 61.75 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "5.553 ns" { result_t[11] result[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.553 ns" { result_t[11] result[11] } { 0.000ns 3.429ns } { 0.000ns 2.124ns } } }  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "5.553 ns" { result_t[11] result[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.553 ns" { result_t[11] result[11] } { 0.000ns 3.429ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "B\[9\] dinput\[9\] clk -4.113 ns register " "Info: th for register \"B\[9\]\" (data pin = \"dinput\[9\]\", clock pin = \"clk\") is -4.113 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 53; CLK Node = 'clk'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { clk } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns B\[9\] 2 REG LC_X9_Y16_N2 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X9_Y16_N2; Fanout = 6; REG Node = 'B\[9\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.485 ns" { clk B[9] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 B[9] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.082 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns dinput\[9\] 1 PIN PIN_224 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_224; Fanout = 2; PIN Node = 'dinput\[9\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { dinput[9] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.492 ns) + CELL(0.115 ns) 7.082 ns B\[9\] 2 REG LC_X9_Y16_N2 6 " "Info: 2: + IC(5.492 ns) + CELL(0.115 ns) = 7.082 ns; Loc. = LC_X9_Y16_N2; Fanout = 6; REG Node = 'B\[9\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "5.607 ns" { dinput[9] B[9] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 22.45 % " "Info: Total cell delay = 1.590 ns ( 22.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.492 ns 77.55 % " "Info: Total interconnect delay = 5.492 ns ( 77.55 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "7.082 ns" { dinput[9] B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.082 ns" { dinput[9] dinput[9]~out0 B[9] } { 0.000ns 0.000ns 5.492ns } { 0.000ns 1.475ns 0.115ns } } }  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 B[9] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "7.082 ns" { dinput[9] B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.082 ns" { dinput[9] dinput[9]~out0 B[9] } { 0.000ns 0.000ns 5.492ns } { 0.000ns 1.475ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 17 10:23:13 2008 " "Info: Processing ended: Thu Apr 17 10:23:13 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}