alu.tan.qmsg

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 10:23:13 2008 " "Info: Processing started: Thu Apr 17 10:23:13 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off alu -c alu --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alu -c alu --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register A\[0\] register result_t\[1\] 100.49 MHz 9.951 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.49 MHz between source register \"A\[0\]\" and destination register \"result_t\[1\]\" (period= 9.951 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.690 ns + Longest register register " "Info: + Longest register to register delay is 9.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns A\[0\] 1 REG LC_X8_Y15_N1 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y15_N1; Fanout = 14; REG Node = 'A\[0\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { A[0] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.002 ns) + CELL(0.575 ns) 3.577 ns add~1680COUT1_1967 2 COMB LC_X10_Y15_N2 2 " "Info: 2: + IC(3.002 ns) + CELL(0.575 ns) = 3.577 ns; Loc. = LC_X10_Y15_N2; Fanout = 2; COMB Node = 'add~1680COUT1_1967'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "3.577 ns" { A[0] add~1680COUT1_1967 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 4.185 ns add~1693 3 COMB LC_X10_Y15_N3 1 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 4.185 ns; Loc. = LC_X10_Y15_N3; Fanout = 1; COMB Node = 'add~1693'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.608 ns" { add~1680COUT1_1967 add~1693 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.216 ns) + CELL(0.114 ns) 5.515 ns Mux~3080 4 COMB LC_X11_Y13_N9 1 " "Info: 4: + IC(1.216 ns) + CELL(0.114 ns) = 5.515 ns; Loc. = LC_X11_Y13_N9; Fanout = 1; COMB Node = 'Mux~3080'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.330 ns" { add~1693 Mux~3080 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.292 ns) 6.243 ns Mux~3081 5 COMB LC_X11_Y13_N6 1 " "Info: 5: + IC(0.436 ns) + CELL(0.292 ns) = 6.243 ns; Loc. = LC_X11_Y13_N6; Fanout = 1; COMB Node = 'Mux~3081'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "0.728 ns" { Mux~3080 Mux~3081 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.442 ns) 8.229 ns Mux~3082 6 COMB LC_X6_Y15_N7 1 " "Info: 6: + IC(1.544 ns) + CELL(0.442 ns) = 8.229 ns; Loc. = LC_X6_Y15_N7; Fanout = 1; COMB Node = 'Mux~3082'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.986 ns" { Mux~3081 Mux~3082 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(0.309 ns) 9.690 ns result_t\[1\] 7 REG LC_X6_Y14_N6 2 " "Info: 7: + IC(1.152 ns) + CELL(0.309 ns) = 9.690 ns; Loc. = LC_X6_Y14_N6; Fanout = 2; REG Node = 'result_t\[1\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.461 ns" { Mux~3082 result_t[1] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.340 ns 24.15 % " "Info: Total cell delay = 2.340 ns ( 24.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.350 ns 75.85 % " "Info: Total interconnect delay = 7.350 ns ( 75.85 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "9.690 ns" { A[0] add~1680COUT1_1967 add~1693 Mux~3080 Mux~3081 Mux~3082 result_t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.690 ns" { A[0] add~1680COUT1_1967 add~1693 Mux~3080 Mux~3081 Mux~3082 result_t[1] } { 0.000ns 3.002ns 0.000ns 1.216ns 0.436ns 1.544ns 1.152ns } { 0.000ns 0.575ns 0.608ns 0.114ns 0.292ns 0.442ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 53; CLK Node = 'clk'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { clk } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns result_t\[1\] 2 REG LC_X6_Y14_N6 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y14_N6; Fanout = 2; REG Node = 'result_t\[1\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.485 ns" { clk result_t[1] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 53 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 53; CLK Node = 'clk'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "" { clk } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns A\[0\] 2 REG LC_X8_Y15_N1 14 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y15_N1; Fanout = 14; REG Node = 'A\[0\]'" {  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "1.485 ns" { clk A[0] } "NODE_NAME" } "" } } { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk A[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 A[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk A[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 A[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "alu.vhd" "" { Text "D:/alu/alu.vhd" 27 -1 0 } }  } 0}  } { { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "9.690 ns" { A[0] add~1680COUT1_1967 add~1693 Mux~3080 Mux~3081 Mux~3082 result_t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.690 ns" { A[0] add~1680COUT1_1967 add~1693 Mux~3080 Mux~3081 Mux~3082 result_t[1] } { 0.000ns 3.002ns 0.000ns 1.216ns 0.436ns 1.544ns 1.152ns } { 0.000ns 0.575ns 0.608ns 0.114ns 0.292ns 0.442ns 0.309ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk result_t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 result_t[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/alu/db/alu_cmp.qrpt" "" { Report "D:/alu/db/alu_cmp.qrpt" Compiler "alu" "UNKNOWN" "V1" "D:/alu/db/alu.quartus_db" { Floorplan "D:/alu/" "" "2.954 ns" { clk A[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 A[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}