alu.vho

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

Mux_a3082_I_modesel <= "1001001010101";
Mux_a3082_I_pathsel <= "00000001111";
result_t_a1_a_aI_modesel <= "1100001010101";
result_t_a1_a_aI_pathsel <= "00000001111";
Z_a154_I_modesel <= "1001001010101";
Z_a154_I_pathsel <= "00000001111";
Mux_a3139_I_modesel <= "1001001010101";
Mux_a3139_I_pathsel <= "00000001111";
Mux_a3141_I_modesel <= "1001001010101";
Mux_a3141_I_pathsel <= "00000001111";
Mux_a3142_I_modesel <= "1001001010101";
Mux_a3142_I_pathsel <= "00000001111";
Mux_a3143_I_modesel <= "1001001010101";
Mux_a3143_I_pathsel <= "00000001111";
Mux_a3144_I_modesel <= "1001001010101";
Mux_a3144_I_pathsel <= "00000001111";
result_t_a12_a_aI_modesel <= "1100001010101";
result_t_a12_a_aI_pathsel <= "00000001111";
Mux_a3151_I_modesel <= "1001001010101";
Mux_a3151_I_pathsel <= "00000001111";
Mux_a3153_I_modesel <= "1001001010101";
Mux_a3153_I_pathsel <= "00000001111";
Mux_a3169_I_modesel <= "1001001010101";
Mux_a3169_I_pathsel <= "00000001111";
Mux_a3170_I_modesel <= "1001001010101";
Mux_a3170_I_pathsel <= "00000001111";
Mux_a3154_I_modesel <= "1001001010101";
Mux_a3154_I_pathsel <= "00000001111";
result_t_a14_a_aI_modesel <= "1100001010101";
result_t_a14_a_aI_pathsel <= "00000001111";
Mux_a3161_I_modesel <= "1001001010101";
Mux_a3161_I_pathsel <= "00000001101";
Mux_a3162_I_modesel <= "1001001010101";
Mux_a3162_I_pathsel <= "00000001111";
Mux_a3158_I_modesel <= "1001001010101";
Mux_a3158_I_pathsel <= "00000001110";
Mux_a3159_I_modesel <= "1001001010101";
Mux_a3159_I_pathsel <= "00000001101";
Mux_a3157_I_modesel <= "1001001010101";
Mux_a3157_I_pathsel <= "00000001111";
Mux_a3160_I_modesel <= "1001001010101";
Mux_a3160_I_pathsel <= "00000001111";
Mux_a3156_I_modesel <= "1001001010101";
Mux_a3156_I_pathsel <= "00000001111";
result_t_a15_a_aI_modesel <= "1100001010101";
result_t_a15_a_aI_pathsel <= "00000001111";
Mux_a3147_I_modesel <= "1001001010101";
Mux_a3147_I_pathsel <= "00000001111";
Mux_a3148_I_modesel <= "1001001010101";
Mux_a3148_I_pathsel <= "00000001111";
Mux_a3149_I_modesel <= "1001001010101";
Mux_a3149_I_pathsel <= "00000001111";
result_t_a13_a_aI_modesel <= "1100001010101";
result_t_a13_a_aI_pathsel <= "00000001111";
Z_a157_I_modesel <= "1001001010101";
Z_a157_I_pathsel <= "00000001111";
Z_a158_I_modesel <= "1001001010101";
Z_a158_I_pathsel <= "00000001111";
z1_tmp_a28_I_modesel <= "1001001010101";
z1_tmp_a28_I_pathsel <= "00000000111";
z1_tmp_aI_modesel <= "1100001010101";
z1_tmp_aI_pathsel <= "00000000110";
Z_areg0_I_modesel <= "1100001010101";
Z_areg0_I_pathsel <= "00000001111";
C_aI_modesel <= "000000000000000000000000010";
Z_aI_modesel <= "000000000000000000000000010";
result_a0_a_aI_modesel <= "000000000000000000000000010";
result_a1_a_aI_modesel <= "000000000000000000000000010";
result_a2_a_aI_modesel <= "000000000000000000000000010";
result_a3_a_aI_modesel <= "000000000000000000000000010";
result_a4_a_aI_modesel <= "000000000000000000000000010";
result_a5_a_aI_modesel <= "000000000000000000000000010";
result_a6_a_aI_modesel <= "000000000000000000000000010";
result_a7_a_aI_modesel <= "000000000000000000000000010";
result_a8_a_aI_modesel <= "000000000000000000000000010";
result_a9_a_aI_modesel <= "000000000000000000000000010";
result_a10_a_aI_modesel <= "000000000000000000000000010";
result_a11_a_aI_modesel <= "000000000000000000000000010";
result_a12_a_aI_modesel <= "000000000000000000000000010";
result_a13_a_aI_modesel <= "000000000000000000000000010";
result_a14_a_aI_modesel <= "000000000000000000000000010";
result_a15_a_aI_modesel <= "000000000000000000000000010";

INV_INST_reset_acombout : INV
PORT MAP (
	 IN1 => reset_acombout,
	 Y => ALT_INV_reset_acombout);

INV_INST_write_acombout : INV
PORT MAP (
	 IN1 => write_acombout,
	 Y => ALT_INV_write_acombout);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

clk_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => clk_aI_modesel,
	combout => clk_acombout,
	padio => ww_clk);

OP_a3_a_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => OP_a3_a_aI_modesel,
	combout => OP_a3_a_acombout,
	padio => ww_OP(3));

OP_a2_a_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => OP_a2_a_aI_modesel,
	combout => OP_a2_a_acombout,
	padio => ww_OP(2));

reduce_or_a11_I : cyclone_lcell
-- Equation(s):
-- reduce_or_a11 = OP_a3_a_acombout & (OP_a2_a_acombout)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "A0A0",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => reduce_or_a11_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => OP_a3_a_acombout,
	datab => VCC,
	datac => OP_a2_a_acombout,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => reduce_or_a11_I_modesel,
	combout => reduce_or_a11);

OP_a1_a_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => OP_a1_a_aI_modesel,
	combout => OP_a1_a_acombout,
	padio => ww_OP(1));

dinput_a12_a_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => dinput_a12_a_aI_modesel,
	combout => dinput_a12_a_acombout,
	padio => ww_dinput(12));

OP_a0_a_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => OP_a0_a_aI_modesel,
	combout => OP_a0_a_acombout,
	padio => ww_OP(0));