alu.vho

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

SIGNAL add_a1885 : std_logic;
SIGNAL add_a1885COUT1_1978 : std_logic;
SIGNAL add_a1905 : std_logic;
SIGNAL add_a1905COUT1_1979 : std_logic;
SIGNAL add_a1919 : std_logic;
SIGNAL add_a1674 : std_logic;
SIGNAL add_a1674COUT1_1954 : std_logic;
SIGNAL add_a1690 : std_logic;
SIGNAL add_a1690COUT1_1955 : std_logic;
SIGNAL add_a1700 : std_logic;
SIGNAL add_a1720 : std_logic;
SIGNAL add_a1720COUT1_1956 : std_logic;
SIGNAL add_a1730 : std_logic;
SIGNAL add_a1730COUT1_1957 : std_logic;
SIGNAL add_a1750 : std_logic;
SIGNAL add_a1750COUT1_1958 : std_logic;
SIGNAL add_a1760 : std_logic;
SIGNAL add_a1760COUT1_1959 : std_logic;
SIGNAL add_a1780 : std_logic;
SIGNAL add_a1790 : std_logic;
SIGNAL add_a1790COUT1_1960 : std_logic;
SIGNAL add_a1810 : std_logic;
SIGNAL add_a1810COUT1_1961 : std_logic;
SIGNAL add_a1820 : std_logic;
SIGNAL add_a1820COUT1_1962 : std_logic;
SIGNAL add_a1840 : std_logic;
SIGNAL add_a1840COUT1_1963 : std_logic;
SIGNAL add_a1850 : std_logic;
SIGNAL add_a1870 : std_logic;
SIGNAL add_a1870COUT1_1964 : std_logic;
SIGNAL add_a1880 : std_logic;
SIGNAL add_a1880COUT1_1965 : std_logic;
SIGNAL add_a1895 : std_logic;
SIGNAL add_a1895COUT1_1966 : std_logic;
SIGNAL add_a1913 : std_logic;
SIGNAL add_a1918 : std_logic;
SIGNAL Mux_a3166 : std_logic;
SIGNAL Mux_a3167 : std_logic;
SIGNAL result_t_a16_a : std_logic;
SIGNAL z1_tmp_a27 : std_logic;
SIGNAL c_tmp : std_logic;
SIGNAL reduce_or_a1 : std_logic;
SIGNAL C_areg0 : std_logic;
SIGNAL result_t_a1_a_a778 : std_logic;
SIGNAL result_t_a2_a_a774 : std_logic;
SIGNAL Mux_a3100 : std_logic;
SIGNAL add_a1738 : std_logic;
SIGNAL result_t_a2_a_a775 : std_logic;
SIGNAL Mux_a3095 : std_logic;
SIGNAL Mux_a3096 : std_logic;
SIGNAL add_a1728 : std_logic;
SIGNAL Mux_a3086 : std_logic;
SIGNAL Mux_a3097 : std_logic;
SIGNAL result_t_a2_a_a776 : std_logic;
SIGNAL result_t_a2_a_a777 : std_logic;
SIGNAL add_a1733 : std_logic;
SIGNAL Mux_a3098 : std_logic;
SIGNAL Mux_a3099 : std_logic;
SIGNAL result_t_a4_a : std_logic;
SIGNAL add_a1743 : std_logic;
SIGNAL result_t_a1_a_a771 : std_logic;
SIGNAL result_t_a1_a_a773 : std_logic;
SIGNAL add_a1748 : std_logic;
SIGNAL add_a1753 : std_logic;
SIGNAL Mux_a3103 : std_logic;
SIGNAL Mux_a3104 : std_logic;
SIGNAL result_t_a1_a_a772 : std_logic;
SIGNAL Mux_a3102 : std_logic;
SIGNAL Mux_a3105 : std_logic;
SIGNAL result_t_a5_a : std_logic;
SIGNAL Mux_a3112 : std_logic;
SIGNAL add_a1783 : std_logic;
SIGNAL Mux_a3113 : std_logic;
SIGNAL add_a1778 : std_logic;
SIGNAL Mux_a3114 : std_logic;
SIGNAL add_a1773 : std_logic;
SIGNAL Mux_a3115 : std_logic;
SIGNAL result_t_a7_a : std_logic;
SIGNAL Mux_a3108 : std_logic;
SIGNAL Mux_a3107 : std_logic;
SIGNAL add_a1758 : std_logic;
SIGNAL Mux_a3109 : std_logic;
SIGNAL add_a1763 : std_logic;
SIGNAL Mux_a3173 : std_logic;
SIGNAL Mux_a3174 : std_logic;
SIGNAL Mux_a3110 : std_logic;
SIGNAL add_a1768 : std_logic;
SIGNAL result_t_a6_a : std_logic;
SIGNAL Z_a155 : std_logic;
SIGNAL add_a1803 : std_logic;
SIGNAL Mux_a3124 : std_logic;
SIGNAL add_a1808 : std_logic;
SIGNAL add_a1813 : std_logic;
SIGNAL Mux_a3125 : std_logic;
SIGNAL Mux_a3126 : std_logic;
SIGNAL Mux_a3127 : std_logic;
SIGNAL result_t_a9_a : std_logic;
SIGNAL add_a1798 : std_logic;
SIGNAL Mux_a3122 : std_logic;
SIGNAL Mux_a3117 : std_logic;
SIGNAL Mux_a3118 : std_logic;
SIGNAL add_a1788 : std_logic;
SIGNAL Mux_a3119 : std_logic;
SIGNAL add_a1793 : std_logic;
SIGNAL Mux_a3120 : std_logic;
SIGNAL Mux_a3121 : std_logic;
SIGNAL result_t_a8_a : std_logic;
SIGNAL add_a1828 : std_logic;
SIGNAL add_a1823 : std_logic;
SIGNAL Mux_a3129 : std_logic;
SIGNAL add_a1818 : std_logic;
SIGNAL Mux_a3130 : std_logic;
SIGNAL Mux_a3131 : std_logic;
SIGNAL Mux_a3171 : std_logic;
SIGNAL Mux_a3172 : std_logic;
SIGNAL Mux_a3132 : std_logic;
SIGNAL result_t_a10_a : std_logic;
SIGNAL add_a1843 : std_logic;
SIGNAL Mux_a3135 : std_logic;
SIGNAL add_a1838 : std_logic;
SIGNAL Mux_a3136 : std_logic;
SIGNAL add_a1833 : std_logic;
SIGNAL Mux_a3137 : std_logic;
SIGNAL Mux_a3134 : std_logic;
SIGNAL result_t_a11_a : std_logic;
SIGNAL Z_a156 : std_logic;
SIGNAL add_a1671 : std_logic;
SIGNAL Mux_a3074 : std_logic;
SIGNAL Mux_a3075 : std_logic;
SIGNAL Mux_a3076 : std_logic;
SIGNAL Mux_a3177 : std_logic;
SIGNAL Mux_a3178 : std_logic;
SIGNAL result_t_a0_a : std_logic;
SIGNAL add_a1703 : std_logic;
SIGNAL Mux_a3085 : std_logic;
SIGNAL add_a1698 : std_logic;
SIGNAL Mux_a3084 : std_logic;
SIGNAL Mux_a3087 : std_logic;
SIGNAL Mux_a3175 : std_logic;
SIGNAL Mux_a3176 : std_logic;
SIGNAL Mux_a3088 : std_logic;
SIGNAL add_a1708 : std_logic;
SIGNAL result_t_a2_a : std_logic;
SIGNAL Mux_a3090 : std_logic;
SIGNAL add_a1713 : std_logic;
SIGNAL add_a1723 : std_logic;
SIGNAL Mux_a3091 : std_logic;
SIGNAL add_a1718 : std_logic;
SIGNAL Mux_a3092 : std_logic;
SIGNAL Mux_a3093 : std_logic;
SIGNAL result_t_a3_a : std_logic;
SIGNAL add_a1683 : std_logic;
SIGNAL add_a1688 : std_logic;
SIGNAL add_a1693 : std_logic;
SIGNAL Mux_a3080 : std_logic;
SIGNAL Mux_a3081 : std_logic;
SIGNAL Mux_a3079 : std_logic;
SIGNAL Mux_a3082 : std_logic;
SIGNAL result_t_a1_a : std_logic;
SIGNAL Z_a154 : std_logic;
SIGNAL add_a1853 : std_logic;
SIGNAL Mux_a3139 : std_logic;
SIGNAL Mux_a3140 : std_logic;
SIGNAL add_a1848 : std_logic;
SIGNAL Mux_a3141 : std_logic;
SIGNAL Mux_a3142 : std_logic;
SIGNAL Mux_a3143 : std_logic;
SIGNAL add_a1858 : std_logic;
SIGNAL Mux_a3144 : std_logic;
SIGNAL result_t_a12_a : std_logic;
SIGNAL add_a1888 : std_logic;
SIGNAL Mux_a3151 : std_logic;
SIGNAL add_a1878 : std_logic;
SIGNAL Mux_a3152 : std_logic;
SIGNAL Mux_a3153 : std_logic;
SIGNAL add_a1883 : std_logic;
SIGNAL Mux_a3169 : std_logic;
SIGNAL Mux_a3170 : std_logic;
SIGNAL Mux_a3154 : std_logic;
SIGNAL result_t_a14_a : std_logic;
SIGNAL add_a1898 : std_logic;
SIGNAL Mux_a3161 : std_logic;
SIGNAL Mux_a3162 : std_logic;
SIGNAL add_a1903 : std_logic;
SIGNAL add_a1893 : std_logic;
SIGNAL Mux_a3158 : std_logic;
SIGNAL Mux_a3159 : std_logic;
SIGNAL Mux_a3157 : std_logic;
SIGNAL Mux_a3160 : std_logic;
SIGNAL Mux_a3156 : std_logic;
SIGNAL result_t_a15_a : std_logic;
SIGNAL add_a1863 : std_logic;
SIGNAL Mux_a3146 : std_logic;
SIGNAL add_a1873 : std_logic;
SIGNAL Mux_a3147 : std_logic;
SIGNAL add_a1868 : std_logic;
SIGNAL Mux_a3148 : std_logic;
SIGNAL Mux_a3149 : std_logic;
SIGNAL result_t_a13_a : std_logic;
SIGNAL Z_a157 : std_logic;
SIGNAL Z_a158 : std_logic;
SIGNAL z1_tmp_a28 : std_logic;
SIGNAL z1_tmp : std_logic;
SIGNAL Z_areg0 : std_logic;
SIGNAL ALT_INV_reset_acombout : std_logic;
SIGNAL ALT_INV_write_acombout : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	PATHSEL : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	ENABLE_ASYNCH_ARCS : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_OP <= OP;
ww_clk <= clk;
ww_reset <= reset;
ww_write <= write;
ww_dinput <= dinput;
ww_sel <= sel;
C <= ww_C;
Z <= ww_Z;
result <= ww_result;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

clk_aI_modesel <= "000000000000000000000000001";
OP_a3_a_aI_modesel <= "000000000000000000000000001";
OP_a2_a_aI_modesel <= "000000000000000000000000001";
reduce_or_a11_I_modesel <= "1001001010101";
reduce_or_a11_I_pathsel <= "00000000101";
OP_a1_a_aI_modesel <= "000000000000000000000000001";
dinput_a12_a_aI_modesel <= "000000000000000000000000001";
OP_a0_a_aI_modesel <= "000000000000000000000000001";
write_aI_modesel <= "000000000000000000000000001";
reset_aI_modesel <= "000000000000000000000000001";
sel_aI_modesel <= "000000000000000000000000001";
B_a0_a_a109_I_modesel <= "1001001010101";
B_a0_a_a109_I_pathsel <= "00000001101";
B_a12_a_aI_modesel <= "0010100011001";
B_a12_a_aI_pathsel <= "00000101000";
A_a0_a_a134_I_modesel <= "1001001010101";
A_a0_a_a134_I_pathsel <= "00000001101";
A_a12_a_aI_modesel <= "0010100011001";
A_a12_a_aI_pathsel <= "00000101011";
dinput_a7_a_aI_modesel <= "000000000000000000000000001";
B_a7_a_aI_modesel <= "0010100011001";
B_a7_a_aI_pathsel <= "00000101000";
A_a7_a_aI_modesel <= "0010100011001";
A_a7_a_aI_pathsel <= "00000101011";
dinput_a2_a_aI_modesel <= "000000000000000000000000001";
B_a2_a_aI_modesel <= "0010100011001";
B_a2_a_aI_pathsel <= "00000101000";
A_a2_a_aI_modesel <= "0010100011001";
A_a2_a_aI_pathsel <= "00000101011";
dinput_a1_a_aI_modesel <= "000000000000000000000000001";
B_a1_a_aI_modesel <= "0010100011001";
B_a1_a_aI_pathsel <= "00000100001";
A_a1_a_aI_modesel <= "0010100011001";
A_a1_a_aI_pathsel <= "00000101011";
dinput_a0_a_aI_modesel <= "000000000000000000000000001";
B_a0_a_aI_modesel <= "0010100011001";
B_a0_a_aI_pathsel <= "00000100001";
add_a1666_I_modesel <= "1001001010110";