alu.vho

实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

-- DATE "04/17/2008 10:23:17"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	alu IS
    PORT (
	OP : IN std_logic_vector(3 DOWNTO 0);
	clk : IN std_logic;
	reset : IN std_logic;
	write : IN std_logic;
	dinput : IN std_logic_vector(15 DOWNTO 0);
	sel : IN std_logic;
	C : OUT std_logic;
	Z : OUT std_logic;
	result : OUT std_logic_vector(15 DOWNTO 0)
	);
END alu;

ARCHITECTURE structure OF alu IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_OP : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_write : std_logic;
SIGNAL ww_dinput : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_sel : std_logic;
SIGNAL ww_C : std_logic;
SIGNAL ww_Z : std_logic;
SIGNAL ww_result : std_logic_vector(15 DOWNTO 0);
SIGNAL clk_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a3_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a2_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL reduce_or_a11_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL reduce_or_a11_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL OP_a1_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL dinput_a12_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a0_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL write_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL reset_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL sel_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a0_a_a109_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a0_a_a109_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_a12_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a12_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a0_a_a134_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a0_a_a134_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a12_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a12_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a7_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a2_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a1_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a0_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1666_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1666_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1672_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1672_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1677_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1677_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1678_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1678_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3077_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3077_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1683_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1683_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1708_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1708_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a6_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a5_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a4_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a3_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1713_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1713_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1738_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1738_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1743_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1743_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1768_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1768_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1773_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1773_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a11_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a11_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a11_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a11_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a11_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a10_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a10_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a10_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a10_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a10_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a9_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a9_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a9_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a9_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a9_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a8_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a8_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a8_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a8_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a8_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1798_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1798_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1803_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1803_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1828_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1828_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1833_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1833_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1858_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1858_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a15_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL A_a15_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a15_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_a15_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a15_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a14_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a14_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a14_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a14_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a14_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL dinput_a13_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_a13_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_a13_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_a13_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_a13_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1863_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1863_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1888_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1888_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1898_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1898_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1908_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1908_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3165_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3165_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1693_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1693_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1703_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1703_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1723_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1723_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1733_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1733_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1753_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1753_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1763_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1763_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1783_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1783_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1793_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1793_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1813_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1813_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1823_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1823_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1843_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1843_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1853_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1853_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1873_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1873_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1883_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1883_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1903_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1903_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1919_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1919_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1688_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1688_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1698_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1698_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1718_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1718_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1728_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1728_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1748_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1748_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1758_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1758_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1778_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1778_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1788_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1788_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1808_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1808_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1818_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1818_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1838_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1838_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1848_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1848_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1868_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1868_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1878_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1878_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1893_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1893_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1913_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1913_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1918_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1918_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3166_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3166_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3167_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3167_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a16_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a16_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL z1_tmp_a27_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL z1_tmp_a27_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL c_tmp_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL c_tmp_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL reduce_or_a1_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL reduce_or_a1_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL C_areg0_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL C_areg0_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a1_a_a778_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a1_a_a778_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a2_a_a774_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a2_a_a774_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3100_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3100_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a2_a_a775_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a2_a_a775_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3095_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3095_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3086_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3086_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3097_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3097_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a2_a_a776_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a2_a_a776_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a2_a_a777_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a2_a_a777_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3098_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3098_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3099_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3099_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a1_a_a771_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a1_a_a771_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a1_a_a773_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a1_a_a773_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3103_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3103_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3104_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3104_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a1_a_a772_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a1_a_a772_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a3105_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a3105_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);