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📄 alu.vho

📁 实现16种运算的alu,包括+,-,+1,-1,与或非以及移位比较运算。经调试成功。
💻 VHO
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OP_a2_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(2),
	combout => OP_a2_a_acombout);

reduce_or_a11_I : cyclone_lcell
-- Equation(s):
-- reduce_or_a11 = OP_a3_a_acombout & (OP_a2_a_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "A0A0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => OP_a3_a_acombout,
	datac => OP_a2_a_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => reduce_or_a11);

OP_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(1),
	combout => OP_a1_a_acombout);

dinput_a12_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(12),
	combout => dinput_a12_a_acombout);

OP_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(0),
	combout => OP_a0_a_acombout);

write_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_write,
	combout => write_acombout);

reset_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_reset,
	combout => reset_acombout);

sel_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_sel,
	combout => sel_acombout);

B_a0_a_a109_I : cyclone_lcell
-- Equation(s):
-- B_a0_a_a109 = write_acombout & (reset_acombout & sel_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "A000",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => write_acombout,
	datac => reset_acombout,
	datad => sel_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => B_a0_a_a109);

B_a12_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1936 = B[12] & !OP_a0_a_acombout
-- B_a12_a = DFFEAS(add_a1936, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a12_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a12_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1936,
	regout => B_a12_a);

A_a0_a_a134_I : cyclone_lcell
-- Equation(s):
-- A_a0_a_a134 = write_acombout & (reset_acombout & !sel_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00A0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => write_acombout,
	datac => reset_acombout,
	datad => sel_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => A_a0_a_a134);

A_a12_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3140 = OP_a2_a_acombout & !B_a12_a & (A[12] # !OP_a0_a_acombout)
-- A_a12_a = DFFEAS(Mux_a3140, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a12_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00C4",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a0_a_acombout,
	datab => OP_a2_a_acombout,
	datac => dinput_a12_a_acombout,
	datad => B_a12_a,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3140,
	regout => A_a12_a);

dinput_a7_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(7),
	combout => dinput_a7_a_acombout);

B_a7_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1931 = B[7] & !OP_a0_a_acombout
-- B_a7_a = DFFEAS(add_a1931, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a7_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a7_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1931,
	regout => B_a7_a);

A_a7_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3112 = B_a7_a & (A[7] & (!OP_a1_a_acombout) # !A[7] & OP_a0_a_acombout) # !B_a7_a & (OP_a0_a_acombout & A[7] # !OP_a0_a_acombout & (OP_a1_a_acombout))
-- A_a7_a = DFFEAS(Mux_a3112, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a7_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "39E8",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a0_a_acombout,
	datab => B_a7_a,
	datac => dinput_a7_a_acombout,
	datad => OP_a1_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3112,
	regout => A_a7_a);

dinput_a2_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(2),
	combout => dinput_a2_a_acombout);

B_a2_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1926 = B[2] & !OP_a0_a_acombout
-- B_a2_a = DFFEAS(add_a1926, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a2_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a2_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1926,
	regout => B_a2_a);

A_a2_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3085 = !B_a2_a & OP_a2_a_acombout & (A[2] # !OP_a0_a_acombout)
-- A_a2_a = DFFEAS(Mux_a3085, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a2_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "4044",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => B_a2_a,
	datab => OP_a2_a_acombout,
	datac => dinput_a2_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3085,
	regout => A_a2_a);

dinput_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(1),
	combout => dinput_a1_a_acombout);
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