📄 madcat100.rpt
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| | | | | | | | | +------------- LC23 |lpm_add_sub:246|addcore:adder|result_node7
| | | | | | | | | | +----------- LC17 out0
| | | | | | | | | | | +--------- LC18 out2
| | | | | | | | | | | | +------- LC19 out3
| | | | | | | | | | | | | +----- LC20 out4
| | | | | | | | | | | | | | +--- LC21 out7
| | | | | | | | | | | | | | | +- LC22 ~222~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC31 -> - - - - - - - - - - - - * - - - | - * | <-- |lpm_add_sub:245|addcore:adder|result_node3
LC29 -> - - - - - - - - - - - - - * - - | - * | <-- |lpm_add_sub:245|addcore:adder|result_node4
LC24 -> - - - - - - - - - - - - - - * - | - * | <-- |lpm_add_sub:245|addcore:adder|result_node7
LC25 -> - - - - - - - - - - - - * - - - | - * | <-- |lpm_add_sub:246|addcore:adder|result_node3
LC28 -> - - - - - - - - - - - - - * - - | - * | <-- |lpm_add_sub:246|addcore:adder|result_node4
LC23 -> - - - - - - - - - - - - - - * - | - * | <-- |lpm_add_sub:246|addcore:adder|result_node7
LC17 -> * * * * * * * * * * * * * * * * | * * | <-- out0
LC18 -> * * * * * * * * * * * * * * * * | * * | <-- out2
LC19 -> * * * * * * * * * * * * * * * * | * * | <-- out3
LC20 -> - * * * * - * * * * * * * * * * | * * | <-- out4
LC21 -> - - - - * - - - - * * * * * * * | * * | <-- out7
Pin
4 -> - - - - - - - - - - * * * * * * | * * | <-- add
1 -> - - - - - - - - - - - - - - - - | - - | <-- clear
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
5 -> - - - - - - - - - - * * * * * * | * * | <-- sub
LC6 -> * * * * * * * * * * - * * * * * | * * | <-- out1
LC4 -> - - * * * - - * * * - * * * * * | * * | <-- out5
LC5 -> - - - * * - - - * * - * * * * * | * * | <-- out6
LC7 -> - - - - - - - - - - * * * * * - | - * | <-- ~227~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\v\madcat100.rpt
madcat100
** EQUATIONS **
add : INPUT;
clear : INPUT;
clk : INPUT;
sub : INPUT;
-- Node name is 'out0' = 'oreg0'
-- Equation name is 'out0', location is LC017, type is output.
out0 = DFFE( _EQ001 $ GND, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ001 = add & !out0 & !out2 & !out3 & !out4 & !out7 & !sub
# add & !_LC007 & !out0 & !out7 & !sub
# add & out0 & sub
# !add & out0 & !sub
# !add & !out0 & sub;
-- Node name is 'out1' = 'oreg1'
-- Equation name is 'out1', location is LC006, type is output.
out1 = DFFE( _EQ002 $ !_LC008, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ002 = add & out5 & out6 & !sub & _X001
# add & out0 & out1 & !sub
# add & out7 & !sub
# !out0 & !out1 & !sub;
_X001 = EXP(!out2 & !out3 & !out4);
-- Node name is 'out2' = 'oreg2'
-- Equation name is 'out2', location is LC018, type is output.
out2 = DFFE( _EQ003 $ GND, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ003 = add & !_LC007 & out0 & out1 & !out2 & !out7 & !sub
# !add & !out0 & !out1 & !out2 & sub & _X002
# add & !_LC007 & out2 & !out7 & _X003
# out2 & sub & _X004
# !add & out2 & !sub;
_X002 = EXP(!out3 & !out4 & !out5 & !out6 & !out7);
_X003 = EXP( out0 & out1);
_X004 = EXP(!add & !out0 & !out1);
-- Node name is 'out3' = 'oreg3'
-- Equation name is 'out3', location is LC019, type is output.
out3 = DFFE( _EQ004 $ GND, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ004 = add & _LC031 & !out2 & !out3 & !out4 & !out7 & !sub & _X003
# add & !_LC007 & _LC031 & !out7 & !sub
# !add & _LC025 & sub & _X005
# add & out3 & sub
# !add & out3 & _X006;
_X003 = EXP( out0 & out1);
_X005 = EXP(!out0 & !out1 & !out2 & !out4 & !out5 & !out6 & !out7);
_X006 = EXP(!_LC025 & sub);
-- Node name is 'out4' = 'oreg4'
-- Equation name is 'out4', location is LC020, type is output.
out4 = DFFE( _EQ005 $ GND, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ005 = add & _LC029 & !out2 & !out3 & !out4 & !out7 & !sub & _X003
# add & !_LC007 & _LC029 & !out7 & !sub
# !add & _LC028 & sub & _X007
# add & out4 & sub
# !add & out4 & _X008;
_X003 = EXP( out0 & out1);
_X007 = EXP(!out0 & !out1 & !out2 & !out3 & !out5 & !out6 & !out7);
_X008 = EXP(!_LC028 & sub);
-- Node name is 'out5' = 'oreg5'
-- Equation name is 'out5', location is LC004, type is output.
out5 = DFFE( _EQ006 $ _EQ007, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ006 = !add & !_LC030 & sub & _X009
# add & !out5 & sub
# !add & !out5 & !sub;
_X009 = EXP(!out0 & !out1 & !out2 & !out3 & !out4 & !out5 & !out6 & !out7);
_EQ007 = !_LC022 & _X010;
_X010 = EXP( add & !_LC027 & !sub);
-- Node name is 'out6' = 'oreg6'
-- Equation name is 'out6', location is LC005, type is output.
out6 = DFFE( _EQ008 $ _EQ009, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ008 = !add & !_LC032 & sub & _X009
# add & !out6 & sub
# !add & !out6 & !sub;
_X009 = EXP(!out0 & !out1 & !out2 & !out3 & !out4 & !out5 & !out6 & !out7);
_EQ009 = !_LC022 & _X011;
_X011 = EXP( add & !_LC026 & !sub);
-- Node name is 'out7' = 'oreg7'
-- Equation name is 'out7', location is LC021, type is output.
out7 = DFFE( _EQ010 $ GND, GLOBAL( clk), GLOBAL( clear), VCC, VCC);
_EQ010 = add & _LC024 & !out2 & !out3 & !out4 & !out7 & !sub & _X003
# add & !_LC007 & _LC024 & !out7 & !sub
# !add & _LC023 & sub & _X012
# add & out7 & sub
# !add & out7 & _X013;
_X003 = EXP( out0 & out1);
_X012 = EXP(!out0 & !out1 & !out2 & !out3 & !out4 & !out5 & !out6);
_X013 = EXP(!_LC023 & sub);
-- Node name is '|lpm_add_sub:245|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( out3 $ _EQ011);
_EQ011 = out0 & out1 & out2;
-- Node name is '|lpm_add_sub:245|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( out4 $ _EQ012);
_EQ012 = out0 & out1 & out2 & out3;
-- Node name is '|lpm_add_sub:245|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( out5 $ _EQ013);
_EQ013 = out0 & out1 & out2 & out3 & out4;
-- Node name is '|lpm_add_sub:245|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( out6 $ _EQ014);
_EQ014 = out0 & out1 & out2 & out3 & out4 & out5;
-- Node name is '|lpm_add_sub:245|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( out7 $ _EQ015);
_EQ015 = out0 & out1 & out2 & out3 & out4 & out5 & out6;
-- Node name is '|lpm_add_sub:246|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( out3 $ _EQ016);
_EQ016 = !out0 & !out1 & !out2;
-- Node name is '|lpm_add_sub:246|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( out4 $ _EQ017);
_EQ017 = !out0 & !out1 & !out2 & !out3;
-- Node name is '|lpm_add_sub:246|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( out5 $ _EQ018);
_EQ018 = !out0 & !out1 & !out2 & !out3 & !out4;
-- Node name is '|lpm_add_sub:246|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( out6 $ _EQ019);
_EQ019 = !out0 & !out1 & !out2 & !out3 & !out4 & !out5;
-- Node name is '|lpm_add_sub:246|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( out7 $ _EQ020);
_EQ020 = !out0 & !out1 & !out2 & !out3 & !out4 & !out5 & !out6;
-- Node name is '~222~1'
-- Equation name is '~222~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ021 $ GND);
_EQ021 = add & out0 & out1 & out5 & out6 & !sub
# add & out4 & out5 & out6 & !sub
# add & out3 & out5 & out6 & !sub
# add & out2 & out5 & out6 & !sub
# add & out7 & !sub;
-- Node name is '~226~1'
-- Equation name is '~226~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ022 $ GND);
_EQ022 = !add & !out0 & out1 & sub
# add & !out1 & sub
# !add & out0 & !out1;
-- Node name is '~227~1'
-- Equation name is '~227~1', location is LC007, type is buried.
-- synthesized logic cell
_LC007 = LCELL( _EQ023 $ GND);
_EQ023 = out5 & out6;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda\v\madcat100.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,584K
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