madcat.v

来自「关于交通灯的汇编程序」· Verilog 代码 · 共 23 行

module  madcat(clk,clear,add,sub,co);
input   clk,clear,add,sub;
output[7:0]  co;
reg[7:0] cnt;
reg d;
assign co=cnt;
always @(posedge clk or negedge clear)
    begin
        if(!clear)        cnt<=8'h00;
                          d<=0;
          else if(add&sub)     cnt<=cnt;
                               d<=d
           else if(add) 
              		if(cnt>=99)  cnt<=d;
              		else     cnt<=cnt+1;
                         d<=cnt;
          else if(sub)    
           		if(cnt<=0)      cnt<=d;
           		else      cnt<=cnt-1;
                         d<=cnt
    end
endmodule