📄 small.fit.qmsg
字号:
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "9 19 " "Info: No exact pin location assignment(s) for 9 pins of 19 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[7\] " "Info: Pin out_port_from_the_led_pio\[7\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[7\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[7] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[6\] " "Info: Pin out_port_from_the_led_pio\[6\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[6\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[6] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[5\] " "Info: Pin out_port_from_the_led_pio\[5\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[5\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[5] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[4\] " "Info: Pin out_port_from_the_led_pio\[4\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[4\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[4] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[3\] " "Info: Pin out_port_from_the_led_pio\[3\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[3\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[3] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[2\] " "Info: Pin out_port_from_the_led_pio\[2\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[2\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[2] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[1\] " "Info: Pin out_port_from_the_led_pio\[1\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[1\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[1] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out_port_from_the_led_pio\[0\] " "Info: Pin out_port_from_the_led_pio\[0\] not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 320 624 800 336 "out_port_from_the_led_pio\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out_port_from_the_led_pio\[0\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { out_port_from_the_led_pio[0] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { out_port_from_the_led_pio[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pld_clear_n " "Info: Pin pld_clear_n not assigned to an exact location on the device" { } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 288 24 192 304 "pld_clear_n" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pld_clear_n" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { pld_clear_n } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { pld_clear_n } "NODE_NAME" } } } 0} } { } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "osc_clk\[0\] (placed in PIN P25 (CLK6, LVDSCLK3p, Input)) " "Info: Automatically promoted node osc_clk\[0\] (placed in PIN P25 (CLK6, LVDSCLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" { } { } 0} } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "osc_clk\[0\]" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { osc_clk[0] } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { osc_clk[0] } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "dividef:inst2\|reduce_nor~0 " "Info: Automatically promoted node dividef:inst2\|reduce_nor~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~391 " "Info: Destination node dividef:inst2\|COUNT~391" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~391" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~391 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~391 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~392 " "Info: Destination node dividef:inst2\|COUNT~392" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~392" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~392 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~392 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~393 " "Info: Destination node dividef:inst2\|COUNT~393" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~393" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~393 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~393 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~394 " "Info: Destination node dividef:inst2\|COUNT~394" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~394" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~394 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~394 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~395 " "Info: Destination node dividef:inst2\|COUNT~395" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~395" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~395 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~395 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~396 " "Info: Destination node dividef:inst2\|COUNT~396" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~396" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~396 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~396 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~397 " "Info: Destination node dividef:inst2\|COUNT~397" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~397" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~397 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~397 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~398 " "Info: Destination node dividef:inst2\|COUNT~398" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~398" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~398 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~398 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~399 " "Info: Destination node dividef:inst2\|COUNT~399" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~399" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~399 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~399 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dividef:inst2\|COUNT~400 " "Info: Destination node dividef:inst2\|COUNT~400" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT~400" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|COUNT~400 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|COUNT~400 } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0} } { } 0} } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~0" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { dividef:inst2|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { dividef:inst2|reduce_nor~0 } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pld_clear_n (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node pld_clear_n (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0} } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 288 24 192 304 "pld_clear_n" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pld_clear_n" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { pld_clear_n } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { pld_clear_n } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "small_2C35:inst\|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch\|data_out " "Info: Automatically promoted node small_2C35:inst\|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "small_2C35:inst\|cpu:the_cpu\|W_rf_wren_a " "Info: Destination node small_2C35:inst\|cpu:the_cpu\|W_rf_wren_a" { } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 709 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "small_2C35:inst\|cpu:the_cpu\|W_rf_wren_a" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { small_2C35:inst|cpu:the_cpu|W_rf_wren_a } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { small_2C35:inst|cpu:the_cpu|W_rf_wren_a } "NODE_NAME" } } } 0} } { } 0} } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 821 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "small_2C35:inst\|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch\|data_out" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { small_2C35:inst|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch|data_out } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { small_2C35:inst|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch|data_out } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29" { } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~29 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~29 } "NODE_NAME" } } } 0} } { } 0} } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0" } } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { sld_hub:sld_hub_inst|CLEAR_SIGNAL~0 } "NODE_NAME" } "" } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.fld" "" "" { sld_hub:sld_hub_inst|CLEAR_SIGNAL~0 } "NODE_NAME" } } } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -