small.map.qmsg

38译码器的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 11:22:11 2006 " "Info: Processing started: Sat Aug 19 11:22:11 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off small -c small " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off small -c small" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DFFLOP.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DFFLOP.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DFFLOP-FFA " "Info: Found design unit 1: DFFLOP-FFA" {  } { { "DFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/DFFLOP.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DFFLOP " "Info: Found entity 1: DFFLOP" {  } { { "DFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/DFFLOP.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dividef.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dividef.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dividef-DIVIDE_arch " "Info: Found design unit 1: dividef-DIVIDE_arch" {  } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dividef " "Info: Found entity 1: dividef" {  } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "small.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file small.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 small " "Info: Found entity 1: small" {  } { { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TFFLOP.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TFFLOP.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TFFLOP-FFB " "Info: Found design unit 1: TFFLOP-FFB" {  } { { "TFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/TFFLOP.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 TFFLOP " "Info: Found entity 1: TFFLOP" {  } { { "TFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/TFFLOP.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altera_vhdl_support.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file altera_vhdl_support.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_vhdl_support_lib " "Info: Found design unit 1: altera_vhdl_support_lib" {  } { { "altera_vhdl_support.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/altera_vhdl_support.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 altera_vhdl_support_lib-body " "Info: Found design unit 2: altera_vhdl_support_lib-body" {  } { { "altera_vhdl_support.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/altera_vhdl_support.vhd" 110 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "small " "Info: Elaborating entity \"small\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DFFLOP DFFLOP:inst3 " "Info: Elaborating entity \"DFFLOP\" for hierarchy \"DFFLOP:inst3\"" {  } { { "small.bdf" "inst3" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 488 400 496 616 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dividef dividef:inst2 " "Info: Elaborating entity \"dividef\" for hierarchy \"dividef:inst2\"" {  } { { "small.bdf" "inst2" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 424 248 360 520 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TFFLOP TFFLOP:inst4 " "Info: Elaborating entity \"TFFLOP\" for hierarchy \"TFFLOP:inst4\"" {  } { { "small.bdf" "inst4" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 584 504 600 680 "inst4" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Q_S TFFLOP.vhd(31) " "Warning: VHDL Process Statement warning at TFFLOP.vhd(31): signal \"Q_S\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/TFFLOP.vhd" 31 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "small_2C35.vhd 12 6 " "Info: Using design file small_2C35.vhd, which is not specified as a design file for the current project, but contains definitions for 12 design units and 6 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_data_master_arbitrator-europa " "Info: Found design unit 1: cpu_data_master_arbitrator-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 58 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu_instruction_master_arbitrator-europa " "Info: Found design unit 2: cpu_instruction_master_arbitrator-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 135 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 led_pio_s1_arbitrator-europa " "Info: Found design unit 3: led_pio_s1_arbitrator-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 275 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 onchip_ram_s1_arbitrator-europa " "Info: Found design unit 4: onchip_ram_s1_arbitrator-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 479 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 small_2C35_reset_clk_domain_synch_module-europa " "Info: Found design unit 5: small_2C35_reset_clk_domain_synch_module-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 826 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 small_2C35-europa " "Info: Found design unit 6: small_2C35-europa" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 882 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_data_master_arbitrator " "Info: Found entity 1: cpu_data_master_arbitrator" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_instruction_master_arbitrator " "Info: Found entity 2: cpu_instruction_master_arbitrator" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 111 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 led_pio_s1_arbitrator " "Info: Found entity 3: led_pio_s1_arbitrator" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 246 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 onchip_ram_s1_arbitrator " "Info: Found entity 4: onchip_ram_s1_arbitrator" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 440 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 small_2C35_reset_clk_domain_synch_module " "Info: Found entity 5: small_2C35_reset_clk_domain_synch_module" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 813 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 small_2C35 " "Info: Found entity 6: small_2C35" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 870 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_2C35 small_2C35:inst " "Info: Elaborating entity \"small_2C35\" for hierarchy \"small_2C35:inst\"" {  } { { "small.bdf" "inst" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 248 288 544 360 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_data_master_arbitrator small_2C35:inst\|cpu_data_master_arbitrator:the_cpu_data_master " "Info: Elaborating entity \"cpu_data_master_arbitrator\" for hierarchy \"small_2C35:inst\|cpu_data_master_arbitrator:the_cpu_data_master\"" {  } { { "small_2C35.vhd" "the_cpu_data_master" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1111 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_instruction_master_arbitrator small_2C35:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master " "Info: Elaborating entity \"cpu_instruction_master_arbitrator\" for hierarchy \"small_2C35:inst\|cpu_instruction_master_arbitrator:the_cpu_instruction_master\"" {  } { { "small_2C35.vhd" "the_cpu_instruction_master" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1138 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time small_2C35.vhd(136) " "Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(136): object \"active_and_waiting_last_time\" declared but not used" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 136 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_instruction_master_address_last_time small_2C35.vhd(137) " "Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(137): object \"cpu_instruction_master_address_last_time\" declared but not used" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 137 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_instruction_master_read_last_time small_2C35.vhd(138) " "Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(138): object \"cpu_instruction_master_read_last_time\" declared but not used" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 138 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu.vhd 4 2 " "Info: Using design file cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_rf_module-europa " "Info: Found design unit 1: cpu_rf_module-europa" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu-europa " "Info: Found design unit 2: cpu-europa" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 178 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_rf_module " "Info: Found entity 1: cpu_rf_module" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu " "Info: Found entity 2: cpu" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 155 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu small_2C35:inst\|cpu:the_cpu " "Info: Elaborating entity \"cpu\" for hierarchy \"small_2C35:inst\|cpu:the_cpu\"" {  } { { "small_2C35.vhd" "the_cpu" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1157 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_test_bench.vhd 2 1 " "Info: Using design file cpu_test_bench.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_test_bench-europa " "Info: Found design unit 1: cpu_test_bench-europa" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 57 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_test_bench " "Info: Found entity 1: cpu_test_bench" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_test_bench small_2C35:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench " "Info: Elaborating entity \"cpu_test_bench\" for hierarchy \"small_2C35:inst\|cpu:the_cpu\|cpu_test_bench:the_cpu_test_bench\"" {  } { { "cpu.vhd" "the_cpu_test_bench" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 770 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "D_inst cpu_test_bench.vhd(58) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(58): object \"D_inst\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 58 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_vinst cpu_test_bench.vhd(187) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(187): object \"W_vinst\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 187 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_0_is_x cpu_test_bench.vhd(188) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(188): object \"av_ld_data_aligned_unfiltered_0_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 188 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_10_is_x cpu_test_bench.vhd(189) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(189): object \"av_ld_data_aligned_unfiltered_10_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 189 0 0 } }  } 0}