tfflop.vhd

38译码器的设计

--- T flip flop

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TFFLOP IS
          PORT (
                    T: in STD_LOGIC;
                    CLK: in  STD_LOGIC;
                    QT: OUT STD_LOGIC
          );
END TFFLOP;
 
ARCHITECTURE FFB OF TFFLOP IS
SIGNAL Q_S:STD_LOGIC;

BEGIN

PROCESS(CLK,T)

BEGIN
IF CLK'EVENT AND CLK='1' THEN
     IF T='1' THEN
        Q_S<=NOT Q_S;
ELSE
        Q_S<=Q_S;
END IF;
END IF;

QT<=Q_S;
END PROCESS;

END FFB;