small.tan.rpt.htm

38译码器的设计

<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.880 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.72 MHz ( period = 6.108 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[8]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.899 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.75 MHz ( period = 6.107 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[24]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.910 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.83 MHz ( period = 6.104 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[25]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.852 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">164.23 MHz ( period = 6.089 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[5]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.858 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">164.69 MHz ( period = 6.072 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[10]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.855 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">164.85 MHz ( period = 6.066 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.835 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">164.88 MHz ( period = 6.065 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_shift_rot_cnt[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.821 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.23 MHz ( period = 6.052 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[18]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.799 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.34 MHz ( period = 6.048 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[24]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.829 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.40 MHz ( period = 6.046 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[5]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.815 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.56 MHz ( period = 6.040 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[29]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.814 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.65 MHz ( period = 6.037 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.806 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">165.86 MHz ( period = 6.029 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[10]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.812 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.17 MHz ( period = 6.018 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_alu_sub</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.806 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.36 MHz ( period = 6.011 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.780 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.36 MHz ( period = 6.011 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_retaddr</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.808 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.39 MHz ( period = 6.010 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[12]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_uncond_cti</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.801 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.44 MHz ( period = 6.008 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[8]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.768 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.64 MHz ( period = 6.001 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[9]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.782 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">166.86 MHz ( period = 5.993 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[11]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.777 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.03 MHz ( period = 5.987 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[26]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.748 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.20 MHz ( period = 5.981 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[29]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.733 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.25 MHz ( period = 5.979 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[7]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.748 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.62 MHz ( period = 5.966 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_cmp_result</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.732 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.62 MHz ( period = 5.966 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_shift_rot_cnt[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.723 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">167.98 MHz ( period = 5.953 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[8]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.720 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.07 MHz ( period = 5.950 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[11]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.734 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.10 MHz ( period = 5.949 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.709 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.24 MHz ( period = 5.944 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[3]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.713 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.29 MHz ( period = 5.942 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[11]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.726 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.41 MHz ( period = 5.938 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[5]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[4]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.736 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.46 MHz ( period = 5.936 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_shift_rot_cnt[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.693 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">168.46 MHz ( period = 5.936 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[7]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.705 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>