small.tan.rpt.htm

38译码器的设计

</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">156.05 MHz ( period = 6.408 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.206 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">156.49 MHz ( period = 6.390 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[30]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.157 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">156.62 MHz ( period = 6.385 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[16]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.176 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">156.96 MHz ( period = 6.371 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_logic_op[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_cmp_result</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.170 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.06 MHz ( period = 6.367 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[26]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.150 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.11 MHz ( period = 6.365 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_shift_rot_cnt[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.121 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.43 MHz ( period = 6.352 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.121 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.58 MHz ( period = 6.346 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[8]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.106 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.60 MHz ( period = 6.345 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[22]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.141 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.85 MHz ( period = 6.335 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_shift_rot_cnt[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.091 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">157.90 MHz ( period = 6.333 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_st</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.109 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">158.43 MHz ( period = 6.312 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[13]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.100 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">158.50 MHz ( period = 6.309 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.078 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">158.53 MHz ( period = 6.308 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[26]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.069 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">159.06 MHz ( period = 6.287 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.047 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">159.44 MHz ( period = 6.272 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[26]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.055 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">159.92 MHz ( period = 6.253 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[30]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.042 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">159.92 MHz ( period = 6.253 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[13]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.019 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">160.93 MHz ( period = 6.214 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[19]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.017 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">161.13 MHz ( period = 6.206 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[4]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.997 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">161.32 MHz ( period = 6.199 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[16]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.991 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">161.76 MHz ( period = 6.182 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[2]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.973 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">161.81 MHz ( period = 6.180 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.971 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">161.92 MHz ( period = 6.176 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.945 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">162.26 MHz ( period = 6.163 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[25]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.933 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">162.44 MHz ( period = 6.156 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.925 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">162.73 MHz ( period = 6.145 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_new_inst</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_valid</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.915 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.03 MHz ( period = 6.134 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[5]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_logic_op[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.918 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.16 MHz ( period = 6.129 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[1]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.927 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.27 MHz ( period = 6.125 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[25]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.895 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.35 MHz ( period = 6.122 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[3]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.920 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.59 MHz ( period = 6.113 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.882 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.61 MHz ( period = 6.112 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[3]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">5.881 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">163.64 MHz ( period = 6.111 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[18]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>