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<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[1]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.987 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">139.10 MHz ( period = 7.189 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[3]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.980 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">141.24 MHz ( period = 7.080 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.871 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">142.09 MHz ( period = 7.038 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[15]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.829 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">142.43 MHz ( period = 7.021 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.790 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">144.68 MHz ( period = 6.912 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[4]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.710 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">144.99 MHz ( period = 6.897 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_logic_op[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.681 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">145.18 MHz ( period = 6.888 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[2]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.686 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">145.22 MHz ( period = 6.886 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.684 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">145.26 MHz ( period = 6.884 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.675 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">145.65 MHz ( period = 6.866 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[14]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_uncond_cti</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.657 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.65 MHz ( period = 6.773 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_logic_op[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.557 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_we_reg</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_address_reg0</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_address_reg1</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_address_reg2</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_address_reg3</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">147.73 MHz ( period = 6.769 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ram_block1a1~portb_address_reg4</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[28]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.476 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">148.32 MHz ( period = 6.742 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.533 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">149.63 MHz ( period = 6.683 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.452 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">150.58 MHz ( period = 6.641 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[30]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[30]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.430 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">151.15 MHz ( period = 6.616 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[14]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.383 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">151.35 MHz ( period = 6.607 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[1]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.405 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">151.52 MHz ( period = 6.600 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_retaddr</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.390 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">151.52 MHz ( period = 6.600 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[3]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.398 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">151.65 MHz ( period = 6.594 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src1[13]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[14]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.385 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">152.88 MHz ( period = 6.541 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[22]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.337 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">152.91 MHz ( period = 6.540 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[3]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.331 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">153.85 MHz ( period = 6.500 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_logic_op[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_cmp_result</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.299 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">154.27 MHz ( period = 6.482 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[22]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.256 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">155.06 MHz ( period = 6.449 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|E_src2[9]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|W_alu_result[30]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.238 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">155.35 MHz ( period = 6.437 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[11]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_ctrl_uncond_cti</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.228 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">155.42 MHz ( period = 6.434 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[4]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.232 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">156.01 MHz ( period = 6.410 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[2]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">6.208 ns</TD>
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