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<H1>Timing Analyzer report for small</H1>
<H3>Wed Apr 20 20:13:08 2005<BR>
Version 5.0 Build 146 04/13/2005 SJ Full Version</H3>
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<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Timing Analyzer Summary</A></LI>
<LI><A HREF="#3">Timing Analyzer Settings</A></LI>
<LI><A HREF="#4">Clock Settings Summary</A></LI>
<LI><A HREF="#5">Clock Setup: 'osc_clk[0]'</A></LI>
<LI><A HREF="#6">tco</A></LI>
<LI><A HREF="#7">Timing Analyzer Messages</A></LI>
</OL>
<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
</PRE>
<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Timing Analyzer Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Type</TH>
<TH>Slack</TH>
<TH>Required Time</TH>
<TH>Actual Time</TH>
<TH>From</TH>
<TH>To</TH>
<TH>From Clock</TH>
<TH>To Clock</TH>
<TH>Failed Paths</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Worst-case tco</TD>
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.704 ns</TD>
<TD ALIGN="LEFT">small_2C35:inst|led_pio:the_led_pio|data_out[3]</TD>
<TD ALIGN="LEFT">out_port_from_the_led_pio[3]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Clock Setup: 'osc_clk[0]'</TD>
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">112.68 MHz ( period = 8.875 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total number of failed paths</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Timing Analyzer Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>From</TH>
<TH>To</TH>
<TH>Entity Name</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device Name</TD>
<TD ALIGN="LEFT">EP2C35F672C6</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Preliminary</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of source nodes to report per destination node</TD>
<TD ALIGN="LEFT">10</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of destination nodes to report</TD>
<TD ALIGN="LEFT">10</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of paths to report</TD>
<TD ALIGN="LEFT">200</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Report Minimum Timing Checks</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use Fast Timing Models</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Report IO Paths Separately</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Default hold multicycle</TD>
<TD ALIGN="LEFT">Same as Multicycle</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Cut paths between unrelated clock domains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Cut off read during write signal paths</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Cut off feedback from I/O pins</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Report Combined Fast/Slow Timing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore Clock Settings</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Analyze latches as synchronous elements</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable Recovery/Removal analysis</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable Clock Latency</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Clock Settings Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Clock Node Name</TH>
<TH>Clock Setting Name</TH>
<TH>Type</TH>
<TH>Fmax Requirement</TH>
<TH>Early Latency</TH>
<TH>Late Latency</TH>
<TH>Based on</TH>
<TH>Multiply Base Fmax by</TH>
<TH>Divide Base Fmax by</TH>
<TH>Offset</TH>
<TH>Phase offset</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT">User Pin</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">0.000 ns</TD>
<TD ALIGN="LEFT">0.000 ns</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Clock Setup: 'osc_clk[0]'</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Slack</TH>
<TH>Actual fmax (period)</TH>
<TH>From</TH>
<TH>To</TH>
<TH>From Clock</TH>
<TH>To Clock</TH>
<TH>Required Setup Relationship</TH>
<TH>Required Longest P2P Time</TH>
<TH>Actual Longest P2P Time</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">112.68 MHz ( period = 8.875 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">8.666 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">120.69 MHz ( period = 8.286 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[0]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">8.084 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">128.07 MHz ( period = 7.808 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[2]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.606 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">131.93 MHz ( period = 7.580 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[4]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.371 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">133.32 MHz ( period = 7.501 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[4]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.292 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">133.74 MHz ( period = 7.477 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[2]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.268 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">133.78 MHz ( period = 7.475 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[1]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_dst_regnum[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.266 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">136.76 MHz ( period = 7.312 ns )</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|D_iw[5]</TD>
<TD ALIGN="LEFT">small_2C35:inst|cpu:the_cpu|R_wr_dst_reg</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">None</TD>
<TD ALIGN="LEFT">7.110 ns</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">N/A</TD>
<TD ALIGN="LEFT">138.97 MHz ( period = 7.196 ns )</TD>
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