stp1.stp

来自「38译码器的设计」· STP 代码 · 共 68 行 · 第 1/2 页

<session jtag_chain="Nios II Evaluation Board [USB-0]" jtag_device="@1: EP2C35 (0x020B40DD)" sof_file="small.sof">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2006/08/19 11:21:44  #0">
      <clock name="osc_clk[0]" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="CLR" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="D" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="PSET" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="Q" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="QT" tap_mode="classic" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="CLR" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="D" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="PSET" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="Q" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="QT" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <net is_signal_inverted="no" name="D"/>
          <net is_signal_inverted="no" name="CLR"/>
          <net is_signal_inverted="no" name="PSET"/>
          <net is_signal_inverted="no" name="Q"/>
          <net is_signal_inverted="no" name="QT"/>
        </setup_view>