dfflop.vhd

来自「38译码器的设计」· VHDL 代码 · 共 34 行

-- D flip flop
library IEEE;
use IEEE.std_logic_1164.all;
 
ENTITY DFFLOP IS
          PORT (
                    D: in STD_LOGIC;
                    CLK,CLR,PSET: in STD_LOGIC;
                    Q: out STD_LOGIC
          );
END DFFLOP;
 
ARCHITECTURE FFA OF DFFLOP IS
BEGIN

PROCESS(CLK,PSET,CLR)
BEGIN
IF PSET='1' THEN
  Q<='1';
ELSIF CLR='1' THEN
  Q<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
  Q<=D;
END IF;
END PROCESS;
END FFA;