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<P> --D1_E_shift_rot_result[10] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[10] at LCFF_X46_Y11_N9
<P><A NAME="D1_E_shift_rot_result[10]">D1_E_shift_rot_result[10]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L906">D1L906</A>, <A HREF="#D1_E_src1[10]">D1_E_src1[10]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1_internal_d_read is small_2C35:inst|cpu:the_cpu|internal_d_read at LCFF_X51_Y13_N5
<P><A NAME="D1_internal_d_read">D1_internal_d_read</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1_d_read_nxt">D1_d_read_nxt</A>, <A HREF="#C1L4">C1L4</A>);
<P> --E1L1 is small_2C35:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~35 at LCCOMB_X51_Y14_N4
<P><A NAME="E1L1">E1L1</A> = <A HREF="#E1_cpu_data_master_waitrequest">E1_cpu_data_master_waitrequest</A> # !<A HREF="#D1_internal_d_read">D1_internal_d_read</A> & !<A HREF="#M1_d_write">M1_d_write</A>;
<P> --D1_internal_i_read is small_2C35:inst|cpu:the_cpu|internal_i_read at LCFF_X50_Y14_N3
<P><A NAME="D1_internal_i_read">D1_internal_i_read</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L897">D1L897</A>, <A HREF="#C1L4">C1L4</A>);
<P> --K1_cpu_instruction_master_read_data_valid_onchip_ram_s1 is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|cpu_instruction_master_read_data_valid_onchip_ram_s1 at LCFF_X50_Y14_N11
<P><A NAME="K1_cpu_instruction_master_read_data_valid_onchip_ram_s1">K1_cpu_instruction_master_read_data_valid_onchip_ram_s1</A> = DFFEAS(<A HREF="#K1L81">K1L81</A>, GLOBAL(<A HREF="#A1L3">A1L3</A>), !GLOBAL(<A HREF="#C1L4">C1L4</A>), , , , , , );
<P> --K1_onchip_ram_s1_arb_addend[1] is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|onchip_ram_s1_arb_addend[1] at LCFF_X51_Y15_N17
<P><A NAME="K1_onchip_ram_s1_arb_addend[1]">K1_onchip_ram_s1_arb_addend[1]</A> = DFFEAS(<A HREF="#K1L91">K1L91</A>, GLOBAL(<A HREF="#A1L3">A1L3</A>), !GLOBAL(<A HREF="#C1L4">C1L4</A>), , , , , , );
<P> --K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|cpu_data_master_read_data_valid_onchip_ram_s1_shift_register at LCFF_X51_Y13_N15
<P><A NAME="K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register">K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register</A> = DFFEAS(<A HREF="#K1_registered_cpu_data_master_read_data_valid_onchip_ram_s1">K1_registered_cpu_data_master_read_data_valid_onchip_ram_s1</A>, GLOBAL(<A HREF="#A1L3">A1L3</A>), !GLOBAL(<A HREF="#C1L4">C1L4</A>), , , , , , );
<P> --K1L2 is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|cpu_data_master_qualified_request_onchip_ram_s1~102 at LCCOMB_X51_Y13_N30
<P><A NAME="K1L2">K1L2</A> = <A HREF="#M1_d_write">M1_d_write</A> & !<A HREF="#E1_cpu_data_master_waitrequest">E1_cpu_data_master_waitrequest</A> & (!<A HREF="#D1_internal_d_read">D1_internal_d_read</A> # !<A HREF="#K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register">K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register</A>) # !<A HREF="#M1_d_write">M1_d_write</A> & !<A HREF="#K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register">K1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register</A> & <A HREF="#D1_internal_d_read">D1_internal_d_read</A>;
<P> --K1L3 is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|cpu_data_master_qualified_request_onchip_ram_s1~103 at LCCOMB_X51_Y13_N6
<P><A NAME="K1L3">K1L3</A> = <A HREF="#K1L2">K1L2</A> & !<A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A>;
<P> --K1L1 is small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|add~426 at LCCOMB_X51_Y13_N0
<P><A NAME="K1L1">K1L1</A> = <A HREF="#K1_cpu_instruction_master_read_data_valid_onchip_ram_s1">K1_cpu_instruction_master_read_data_valid_onchip_ram_s1</A> & (!<A HREF="#K1L3">K1L3</A>) # !<A HREF="#K1_cpu_instruction_master_read_data_valid_onchip_ram_s1">K1_cpu_instruction_master_read_data_valid_onchip_ram_s1</A> & (<A HREF="#D1_internal_i_read">D1_internal_i_read</A> & (!<A HREF="#K1L3">K1L3</A>) # !<A HREF="#D1_internal_i_read">D1_internal_i_read</A> & !<A HREF="#K1_onchip_ram_s1_arb_addend[1]">K1_onchip_ram_s1_arb_addend[1]</A> & <A HREF="#K1L3">K1L3</A>);
<P> --E1L2 is small_2C35:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~36 at LCCOMB_X51_Y13_N2
<P><A NAME="E1L2">E1L2</A> = !<A HREF="#E1L1">E1L1</A> & (<A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A> # !<A HREF="#K1L1">K1L1</A> & <A HREF="#K1L2">K1L2</A>);
<P> --D1L025 is small_2C35:inst|cpu:the_cpu|E_logic_result[9]~4758 at LCCOMB_X49_Y13_N6
<P><A NAME="D1L025">D1L025</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[9]">D1_E_src2[9]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_E_src1[9]">D1_E_src1[9]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>);
<P> --D1L887 is small_2C35:inst|cpu:the_cpu|F_pc[7]~33 at LCCOMB_X48_Y14_N16
<P><A NAME="D1L887">D1L887</A> = AMPP_FUNCTION(<A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L23">D1L23</A>, <A HREF="#D1L85">D1L85</A>);
<P> --D1L559 is small_2C35:inst|cpu:the_cpu|W_alu_result[9]~83 at LCCOMB_X49_Y13_N16
<P><A NAME="D1L559">D1L559</A> = AMPP_FUNCTION(<A HREF="#D1L887">D1L887</A>, <A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>, <A HREF="#D1L025">D1L025</A>);
<P> --D1_E_shift_rot_result[9] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[9] at LCFF_X47_Y14_N1
<P><A NAME="D1_E_shift_rot_result[9]">D1_E_shift_rot_result[9]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L806">D1L806</A>, <A HREF="#D1_E_src1[9]">D1_E_src1[9]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1L915 is small_2C35:inst|cpu:the_cpu|E_logic_result[8]~4759 at LCCOMB_X49_Y13_N30
<P><A NAME="D1L915">D1L915</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[8]">D1_E_src2[8]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_E_src1[8]">D1_E_src1[8]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>);
<P> --D1L587 is small_2C35:inst|cpu:the_cpu|F_pc[6]~32 at LCCOMB_X48_Y14_N26
<P><A NAME="D1L587">D1L587</A> = AMPP_FUNCTION(<A HREF="#D1L03">D1L03</A>, <A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L65">D1L65</A>);
<P> --D1L259 is small_2C35:inst|cpu:the_cpu|W_alu_result[8]~84 at LCCOMB_X50_Y13_N4
<P><A NAME="D1L259">D1L259</A> = AMPP_FUNCTION(<A HREF="#D1L915">D1L915</A>, <A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>, <A HREF="#D1L587">D1L587</A>);
<P> --D1_E_shift_rot_result[8] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[8] at LCFF_X47_Y14_N27
<P><A NAME="D1_E_shift_rot_result[8]">D1_E_shift_rot_result[8]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L706">D1L706</A>, <A HREF="#D1_E_src1[8]">D1_E_src1[8]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1L815 is small_2C35:inst|cpu:the_cpu|E_logic_result[7]~4760 at LCCOMB_X49_Y13_N14
<P><A NAME="D1L815">D1L815</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[7]">D1_E_src2[7]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_E_src1[7]">D1_E_src1[7]</A>);
<P> --D1L287 is small_2C35:inst|cpu:the_cpu|F_pc[5]~31 at LCCOMB_X48_Y14_N24
<P><A NAME="D1L287">D1L287</A> = AMPP_FUNCTION(<A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L82">D1L82</A>, <A HREF="#D1L45">D1L45</A>);
<P> --D1L949 is small_2C35:inst|cpu:the_cpu|W_alu_result[7]~85 at LCCOMB_X50_Y13_N24
<P><A NAME="D1L949">D1L949</A> = AMPP_FUNCTION(<A HREF="#D1L815">D1L815</A>, <A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>, <A HREF="#D1L287">D1L287</A>);
<P> --D1_E_shift_rot_result[7] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[7] at LCFF_X47_Y14_N3
<P><A NAME="D1_E_shift_rot_result[7]">D1_E_shift_rot_result[7]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L606">D1L606</A>, <A HREF="#D1_E_src1[7]">D1_E_src1[7]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1L715 is small_2C35:inst|cpu:the_cpu|E_logic_result[6]~4761 at LCCOMB_X49_Y13_N26
<P><A NAME="D1L715">D1L715</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[6]">D1_E_src2[6]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_E_src1[6]">D1_E_src1[6]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>);
<P> --D1L977 is small_2C35:inst|cpu:the_cpu|F_pc[4]~30 at LCCOMB_X48_Y14_N8
<P><A NAME="D1L977">D1L977</A> = AMPP_FUNCTION(<A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L25">D1L25</A>, <A HREF="#D1L62">D1L62</A>);
<P> --D1L649 is small_2C35:inst|cpu:the_cpu|W_alu_result[6]~86 at LCCOMB_X53_Y14_N16
<P><A NAME="D1L649">D1L649</A> = AMPP_FUNCTION(<A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>, <A HREF="#D1L715">D1L715</A>, <A HREF="#D1L977">D1L977</A>);
<P> --D1_E_shift_rot_result[6] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[6] at LCFF_X47_Y14_N11
<P><A NAME="D1_E_shift_rot_result[6]">D1_E_shift_rot_result[6]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L506">D1L506</A>, <A HREF="#D1_E_src1[6]">D1_E_src1[6]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1L615 is small_2C35:inst|cpu:the_cpu|E_logic_result[5]~4762 at LCCOMB_X49_Y12_N12
<P><A NAME="D1L615">D1L615</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[5]">D1_E_src2[5]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_E_src1[5]">D1_E_src1[5]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>);
<P> --D1L794 is small_2C35:inst|cpu:the_cpu|E_arith_result[5]~108 at LCCOMB_X49_Y14_N2
<P><A NAME="D1L794">D1L794</A> = AMPP_FUNCTION(<A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L05">D1L05</A>, <A HREF="#D1L42">D1L42</A>);
<P> --D1L349 is small_2C35:inst|cpu:the_cpu|W_alu_result[5]~87 at LCCOMB_X49_Y14_N24
<P><A NAME="D1L349">D1L349</A> = AMPP_FUNCTION(<A HREF="#D1L615">D1L615</A>, <A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>, <A HREF="#D1L794">D1L794</A>);
<P> --D1_E_shift_rot_result[5] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[5] at LCFF_X47_Y14_N29
<P><A NAME="D1_E_shift_rot_result[5]">D1_E_shift_rot_result[5]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L406">D1L406</A>, <A HREF="#D1_E_src1[5]">D1_E_src1[5]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --D1L515 is small_2C35:inst|cpu:the_cpu|E_logic_result[4]~4763 at LCCOMB_X49_Y12_N2
<P><A NAME="D1L515">D1L515</A> = AMPP_FUNCTION(<A HREF="#D1_E_src2[4]">D1_E_src2[4]</A>, <A HREF="#D1_E_src1[4]">D1_E_src1[4]</A>, <A HREF="#D1_R_logic_op[0]">D1_R_logic_op[0]</A>, <A HREF="#D1_R_logic_op[1]">D1_R_logic_op[1]</A>);
<P> --D1L577 is small_2C35:inst|cpu:the_cpu|F_pc[2]~29 at LCCOMB_X48_Y14_N18
<P><A NAME="D1L577">D1L577</A> = AMPP_FUNCTION(<A HREF="#D1_E_alu_sub">D1_E_alu_sub</A>, <A HREF="#D1L84">D1L84</A>, <A HREF="#D1L22">D1L22</A>);
<P> --D1L049 is small_2C35:inst|cpu:the_cpu|W_alu_result[4]~88 at LCCOMB_X49_Y12_N20
<P><A NAME="D1L049">D1L049</A> = AMPP_FUNCTION(<A HREF="#D1L577">D1L577</A>, <A HREF="#D1L515">D1L515</A>, <A HREF="#D1_R_ctrl_dst_data_sel_logic_result">D1_R_ctrl_dst_data_sel_logic_result</A>);
<P> --D1_E_shift_rot_result[4] is small_2C35:inst|cpu:the_cpu|E_shift_rot_result[4] at LCFF_X49_Y10_N3
<P><A NAME="D1_E_shift_rot_result[4]">D1_E_shift_rot_result[4]</A> = AMPP_FUNCTION(<A HREF="#A1L3">A1L3</A>, <A HREF="#D1L306">D1L306</A>, <A HREF="#D1_E_src1[4]">D1_E_src1[4]</A>, <A HREF="#C1L4">C1L4</A>, <A HREF="#D1_E_new_inst">D1_E_new_inst</A>);
<P> --P1_q_a[1] is small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|q_a[1] at M4K_X52_Y11
<P> --RAM Block Operation Mode: True Dual-Port
<P> --Port A Depth: 32, Port A Width: 18, Port B Depth: 32, Port B Width: 18
<P> --Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
<P> --Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
<P><A NAME="P1_q_a[1]">P1_q_a[1]</A> = AMPP_FUNCTION(<A HREF="#D1_W_rf_wren_a">D1_W_rf_wren_a</A>, <A HREF="#D1_module_input3">D1_module_input3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#D1_W_alu_result[1]">D1_W_alu_result[1]</A>, <A HREF="#D1L708">D1L708</A>, <A HREF="#D1L808">D1L808</A>, <A HREF="#D1L908">D1L908</A>, <A HREF="#D1L018">D1L018</A>, <A HREF="#D1L118">D1L118</A>, <A HREF="#D1_av_ld_byte0_data[1]">D1_av_ld_byte0_data[1]</A>, <A HREF="#D1_D_iw[22]">D1_D_iw[22]</A>, <A HREF="#D1_D_iw[23]">D1_D_iw[23]</A>, <A HREF="#D1_D_iw[24]">D1_D_iw[24]</A>, <A HREF="#D1_D_iw[25]">D1_D_iw[25]</A>, <A HREF="#D1_D_iw[26]">D1_D_iw[26]</A>, GND, GND, GND, GND, GND, GND, <A HREF="#D1_W_alu_result[4]">D1_W_alu_result[4]</A>, <A HREF="#D1_W_alu_result[5]">D1_W_alu_result[5]</A>, <A HREF="#D1_W_alu_result[6]">D1_W_alu_result[6]</A>, <A HREF="#D1_W_alu_result[11]">D1_W_alu_result[11]</A>, <A HREF="#D1_W_alu_result[12]">D1_W_alu_result[12]</A>, <A HREF="#D1_W_alu_result[13]">D1_W_alu_result[13]</A>, <A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A>, <A HREF="#D1_W_alu_result[16]">D1_W_alu_result[16]</A>, <A HREF="#D1_av_ld_byte0_data[4]">D1_av_ld_byte0_data[4]</A>, <A HREF="#D1_av_ld_byte0_data[5]">D1_av_ld_byte0_data[5]</A>, <A HREF="#D1_av_ld_byte0_data[6]">D1_av_ld_byte0_data[6]</A>, <A HREF="#D1_av_ld_byte1_data[3]">D1_av_ld_byte1_data[3]</A>, <A HREF="#D1_av_ld_byte1_data[4]">D1_av_ld_byte1_data[4]</A>, <A HREF="#D1_av_ld_byte1_data[5]">D1_av_ld_byte1_data[5]</A>, <A HREF="#D1_av_ld_byte1_data[6]">D1_av_ld_byte1_data[6]</A>, <A HREF="#D1_av_ld_byte2_data[0]">D1_av_ld_byte2_data[0]</A>, <A HREF="#D1_W_alu_result[17]">D1_W_alu_result[17]</A>, <A HREF="#D1_W_alu_result[23]">D1_W_alu_result[23]</A>, <A HREF="#D1_W_alu_result[24]">D1_W_alu_result[24]</A>, <A HREF="#D1_W_alu_result[25]">D1_W_alu_result[25]</A>, <A HREF="#D1_W_alu_result[26]">D1_W_alu_result[26]</A>, <A HREF="#D1_W_alu_result[28]">D1_W_alu_result[28]</A>, <A HREF="#D1_W_alu_result[29]">D1_W_alu_result[29]</A>, <A HREF="#D1_W_alu_result[30]">D1_W_alu_result[30]</A>, <A HREF="#D1_W_alu_result[31]">D1_W_alu_result[31]</A>, <A HREF="#D1_av_ld_byte2_data[1]">D1_av_ld_byte2_data[1]</A>, <A HREF="#D1_av_ld_byte2_data[7]">D1_av_ld_byte2_data[7]</A>, <A HREF="#D1_av_ld_byte3_data[0]">D1_av_ld_byte3_data[0]</A>, <A HREF="#D1_av_ld_byte3_data[1]">D1_av_ld_byte3_data[1]</A>, <A HREF="#D1_av_ld_byte3_data[2]">D1_av_ld_byte3_data[2]</A>, <A HREF="#D1_av_ld_byte3_data[4]">D1_av_ld_byte3_data[4]</A>, <A HREF="#D1_av_ld_byte3_data[5]">D1_av_ld_byte3_data[5]</A>, <A HREF="#D1_av_ld_byte3_data[6]">D1_av_ld_byte3_data[6]</A>, <A HREF="#D1_av_ld_byte3_data[7]">D1_av_ld_byte3_data[7]</A>);
<P> --P1_q_b[1] is small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|q_b[1] at M4K_X52_Y11
<P><A NAME="P1_q_b[1]">P1_q_b[1]</A> = AMPP_FUNCTION(<A HREF="#D1_W_rf_wren_a">D1_W_rf_wren_a</A>, <A HREF="#D1_module_input3">D1_module_input3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#D1_W_alu_result[1]">D1_W_alu_result[1]</A>, <A HREF="#D1L708">D1L708</A>, <A HREF="#D1L808">D1L808</A>, <A HREF="#D1L908">D1L908</A>, <A HREF="#D1L018">D1L018</A>, <A HREF="#D1L118">D1L118</A>, <A HREF="#D1_av_ld_byte0_data[1]">D1_av_ld_byte0_data[1]</A>, <A HREF="#D1_D_iw[22]">D1_D_iw[22]</A>, <A HREF="#D1_D_iw[23]">D1_D_iw[23]</A>, <A HREF="#D1_D_iw[24]">D1_D_iw[24]</A>, <A HREF="#D1_D_iw[25]">D1_D_iw[25]</A>, <A HREF="#D1_D_iw[26]">D1_D_iw[26]</A>, GND, GND, GND, GND, GND, GND, <A HREF="#D1_W_alu_result[4]">D1_W_alu_result[4]</A>, <A HREF="#D1_W_alu_result[5]">D1_W_alu_result[5]</A>, <A HREF="#D1_W_alu_result[6]">D1_W_alu_result[6]</A>, <A HREF="#D1_W_alu_result[11]">D1_W_alu_result[11]</A>, <A HREF="#D1_W_alu_result[12]">D1_W_alu_result[12]</A>, <A HREF="#D1_W_alu_result[13]">D1_W_alu_result[13]</A>, <A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A>, <A HREF="#D1_W_alu_result[16]">D1_W_alu_result[16]</A>, <A HREF="#D1_av_ld_byte0_data[4]">D1_av_ld_byte0_data[4]</A>, <A HREF="#D1_av_ld_byte0_data[5]">D1_av_ld_byte0_data[5]</A>, <A HREF="#D1_av_ld_byte0_data[6]">D1_av_ld_byte0_data[6]</A>, <A HREF="#D1_av_ld_byte1_data[3]">D1_av_ld_byte1_data[3]</A>, <A HREF="#D1_av_ld_byte1_data[4]">D1_av_ld_byte1_data[4]</A>, <A HREF="#D1_av_ld_byte1_data[5]">D1_av_ld_byte1_data[5]</A>, <A HREF="#D1_av_ld_byte1_data[6]">D1_av_ld_byte1_data[6]</A>, <A HREF="#D1_av_ld_byte2_data[0]">D1_av_ld_byte2_data[0]</A>, <A HREF="#D1_W_alu_result[17]">D1_W_alu_result[17]</A>, <A HREF="#D1_W_alu_result[23]">D1_W_alu_result[23]</A>, <A HREF="#D1_W_alu_result[24]">D1_W_alu_result[24]</A>, <A HREF="#D1_W_alu_result[25]">D1_W_alu_result[25]</A>, <A HREF="#D1_W_alu_result[26]">D1_W_alu_result[26]</A>, <A HREF="#D1_W_alu_result[28]">D1_W_alu_result[28]</A>, <A HREF="#D1_W_alu_result[29]">D1_W_alu_result[29]</A>, <A HREF="#D1_W_alu_result[30]">D1_W_alu_result[30]</A>, <A HREF="#D1_W_alu_result[31]">D1_W_alu_result[31]</A>, <A HREF="#D1_av_ld_byte2_data[1]">D1_av_ld_byte2_data[1]</A>, <A HREF="#D1_av_ld_byte2_data[7]">D1_av_ld_byte2_data[7]</A>, <A HREF="#D1_av_ld_byte3_data[0]">D1_av_ld_byte3_data[0]</A>, <A HREF="#D1_av_ld_byte3_data[1]">D1_av_ld_byte3_data[1]</A>, <A HREF="#D1_av_ld_byte3_data[2]">D1_av_ld_byte3_data[2]</A>, <A HREF="#D1_av_ld_byte3_data[4]">D1_av_ld_byte3_data[4]</A>, <A HREF="#D1_av_ld_byte3_data[5]">D1_av_ld_byte3_data[5]</A>, <A HREF="#D1_av_ld_byte3_data[6]">D1_av_ld_byte3_data[6]</A>, <A HREF="#D1_av_ld_byte3_data[7]">D1_av_ld_byte3_data[7]</A>);
<P> --P1_q_a[16] is small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|q_a[16] at M4K_X52_Y11
<P><A NAME="P1_q_a[16]">P1_q_a[16]</A> = AMPP_FUNCTION(<A HREF="#D1_W_rf_wren_a">D1_W_rf_wren_a</A>, <A HREF="#D1_module_input3">D1_module_input3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#D1_W_alu_result[1]">D1_W_alu_result[1]</A>, <A HREF="#D1L708">D1L708</A>, <A HREF="#D1L808">D1L808</A>, <A HREF="#D1L908">D1L908</A>, <A HREF="#D1L018">D1L018</A>, <A HREF="#D1L118">D1L118</A>, <A HREF="#D1_av_ld_byte0_data[1]">D1_av_ld_byte0_data[1]</A>, <A HREF="#D1_D_iw[22]">D1_D_iw[22]</A>, <A HREF="#D1_D_iw[23]">D1_D_iw[23]</A>, <A HREF="#D1_D_iw[24]">D1_D_iw[24]</A>, <A HREF="#D1_D_iw[25]">D1_D_iw[25]</A>, <A HREF="#D1_D_iw[26]">D1_D_iw[26]</A>, GND, GND, GND, GND, GND, GND, <A HREF="#D1_W_alu_result[4]">D1_W_alu_result[4]</A>, <A HREF="#D1_W_alu_result[5]">D1_W_alu_result[5]</A>, <A HREF="#D1_W_alu_result[6]">D1_W_alu_result[6]</A>, <A HREF="#D1_W_alu_result[11]">D1_W_alu_result[11]</A>, <A HREF="#D1_W_alu_result[12]">D1_W_alu_result[12]</A>, <A HREF="#D1_W_alu_result[13]">D1_W_alu_result[13]</A>, <A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A>, <A HREF="#D1_W_alu_result[16]">D1_W_alu_result[16]</A>, <A HREF="#D1_av_ld_byte0_data[4]">D1_av_ld_byte0_data[4]</A>, <A HREF="#D1_av_ld_byte0_data[5]">D1_av_ld_byte0_data[5]</A>, <A HREF="#D1_av_ld_byte0_data[6]">D1_av_ld_byte0_data[6]</A>, <A HREF="#D1_av_ld_byte1_data[3]">D1_av_ld_byte1_data[3]</A>, <A HREF="#D1_av_ld_byte1_data[4]">D1_av_ld_byte1_data[4]</A>, <A HREF="#D1_av_ld_byte1_data[5]">D1_av_ld_byte1_data[5]</A>, <A HREF="#D1_av_ld_byte1_data[6]">D1_av_ld_byte1_data[6]</A>, <A HREF="#D1_av_ld_byte2_data[0]">D1_av_ld_byte2_data[0]</A>, <A HREF="#D1_W_alu_result[17]">D1_W_alu_result[17]</A>, <A HREF="#D1_W_alu_result[23]">D1_W_alu_result[23]</A>, <A HREF="#D1_W_alu_result[24]">D1_W_alu_result[24]</A>, <A HREF="#D1_W_alu_result[25]">D1_W_alu_result[25]</A>, <A HREF="#D1_W_alu_result[26]">D1_W_alu_result[26]</A>, <A HREF="#D1_W_alu_result[28]">D1_W_alu_result[28]</A>, <A HREF="#D1_W_alu_result[29]">D1_W_alu_result[29]</A>, <A HREF="#D1_W_alu_result[30]">D1_W_alu_result[30]</A>, <A HREF="#D1_W_alu_result[31]">D1_W_alu_result[31]</A>, <A HREF="#D1_av_ld_byte2_data[1]">D1_av_ld_byte2_data[1]</A>, <A HREF="#D1_av_ld_byte2_data[7]">D1_av_ld_byte2_data[7]</A>, <A HREF="#D1_av_ld_byte3_data[0]">D1_av_ld_byte3_data[0]</A>, <A HREF="#D1_av_ld_byte3_data[1]">D1_av_ld_byte3_data[1]</A>, <A HREF="#D1_av_ld_byte3_data[2]">D1_av_ld_byte3_data[2]</A>, <A HREF="#D1_av_ld_byte3_data[4]">D1_av_ld_byte3_data[4]</A>, <A HREF="#D1_av_ld_byte3_data[5]">D1_av_ld_byte3_data[5]</A>, <A HREF="#D1_av_ld_byte3_data[6]">D1_av_ld_byte3_data[6]</A>, <A HREF="#D1_av_ld_byte3_data[7]">D1_av_ld_byte3_data[7]</A>);
<P> --P1_q_a[14] is small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|q_a[14] at M4K_X52_Y11
<P><A NAME="P1_q_a[14]">P1_q_a[14]</A> = AMPP_FUNCTION(<A HREF="#D1_W_rf_wren_a">D1_W_rf_wren_a</A>, <A HREF="#D1_module_input3">D1_module_input3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#A1L3">A1L3</A>, <A HREF="#D1_W_alu_result[1]">D1_W_alu_result[1]</A>, <A HREF="#D1L708">D1L708</A>, <A HREF="#D1L808">D1L808</A>, <A HREF="#D1L908">D1L908</A>, <A HREF="#D1L018">D1L018</A>, <A HREF="#D1L118">D1L118</A>, <A HREF="#D1_av_ld_byte0_data[1]">D1_av_ld_byte0_data[1]</A>, <A HREF="#D1_D_iw[22]">D1_D_iw[22]</A>, <A HREF="#D1_D_iw[23]">D1_D_iw[23]</A>, <A HREF="#D1_D_iw[24]">D1_D_iw[24]</A>, <A HREF="#D1_D_iw[25]">D1_D_iw[25]</A>, <A HREF="#D1_D_iw[26]">D1_D_iw[26]</A>, GND, GND, GND, GND, GND, GND, <A HREF="#D1_W_alu_result[4]">D1_W_alu_result[4]</A>, <A HREF="#D1_W_alu_result[5]">D1_W_alu_result[5]</A>, <A HREF="#D1_W_alu_result[6]">D1_W_alu_result[6]</A>, <A HREF="#D1_W_alu_result[11]">D1_W_alu_result[11]</A>, <A HREF="#D1_W_alu_result[12]">D1_W_alu_result[12]</A>, <A HREF="#D1_W_alu_result[13]">D1_W_alu_result[13]</A>, <A HREF="#D1_W_alu_result[14]">D1_W_alu_result[14]</A>, <A HREF="#D1_W_alu_result[16]">D1_W_alu_result[16]</A>, <A HREF="#D1_av_ld_byte0_data[4]">D1_av_ld_byte0_data[4]</A>, <A HREF="#D1⌨️ 快捷键说明
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