code.syr

16位cpu设计VHDL源码

 Number of Slices:                      49  out of   2352     2%  
 Number of Slice Flip Flops:            64  out of   4704     1%  
 Number of 4 input LUTs:                85  out of   4704     1%  
 Number of bonded IOBs:                 66  out of    170    38%  
 Number of GCLKs:                        4  out of      4   100%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
T1                                 | BUFGP                  | 32    |
RST                                | BUFGP                  | 16    |
PCupdate                           | BUFGP                  | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.684ns (Maximum Frequency: 115.154MHz)
   Minimum input arrival time before clock: 11.756ns
   Maximum output required time after clock: 8.635ns
   Maximum combinational path delay: 14.645ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'T1'
Delay:               8.684ns (Levels of Logic = 18)
  Source:            PC_0 (FF)
  Destination:       PC_15 (FF)
  Source Clock:      T1 rising
  Destination Clock: T1 rising

  Data Path: PC_0 to PC_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            3   1.372   1.628  PC_0 (PC_0)
     LUT1_L:I0->LO         1   0.738   0.000  PC_Madd__n0000_inst_lut2_01 (PC_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.842   0.000  PC_Madd__n0000_inst_cy_0 (PC_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_1 (PC_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_2 (PC_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_3 (PC_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_4 (PC_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_5 (PC_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_6 (PC_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_7 (PC_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_8 (PC_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_9 (PC_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_10 (PC_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_11 (PC_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_12 (PC_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.057   0.000  PC_Madd__n0000_inst_cy_13 (PC_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.057   0.000  PC_Madd__n0000_inst_cy_14 (PC_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.538   1.265  PC_Madd__n0000_inst_sum_15 (PC__n0002<15>)
     LUT3_L:I1->LO         1   0.738   0.000  PC_Mmux__n0001_Result<15>1 (PC__n0001<15>)
     FDCPE:D                   0.765          PC_15
    ----------------------------------------
    Total                      8.684ns (5.791ns logic, 2.893ns route)
                                       (66.7% logic, 33.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'RST'
Delay:               4.486ns (Levels of Logic = 1)
  Source:            PCout_15 (LATCH)
  Destination:       PCout_15 (LATCH)
  Source Clock:      RST falling
  Destination Clock: RST falling

  Data Path: PCout_15 to PCout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  PCout_15 (PCout_15)
     LUT3:I1->O            1   0.738   0.000  Mmux__n0006_Result<15>1 (_n0006<15>)
     LDE:D                     0.765          PCout_15
    ----------------------------------------
    Total                      4.486ns (3.012ns logic, 1.474ns route)
                                       (67.1% logic, 32.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'T1'
Offset:              11.756ns (Levels of Logic = 2)
  Source:            PCupdate (PAD)
  Destination:       IRout_15 (FF)
  Destination Clock: T1 rising

  Data Path: PCupdate to IRout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           67   0.885   6.105  PCupdate_BUFGP (PCupdate_BUFGP)
     LUT3:I2->O           16   0.738   3.080  _n00071 (_n0007)
     FDE:CE                    0.948          IRout_0
    ----------------------------------------
    Total                     11.756ns (2.571ns logic, 9.185ns route)
                                       (21.9% logic, 78.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'RST'
Offset:              11.756ns (Levels of Logic = 2)
  Source:            PCupdate (PAD)
  Destination:       PCout_15 (LATCH)
  Destination Clock: RST falling

  Data Path: PCupdate to PCout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           67   0.885   6.105  PCupdate_BUFGP (PCupdate_BUFGP)
     LUT1:I0->O           16   0.738   3.080  PCout_0__n00011 (PCout_0__n0001)
     LDE:GE                    0.948          PCout_0
    ----------------------------------------
    Total                     11.756ns (2.571ns logic, 9.185ns route)
                                       (21.9% logic, 78.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'PCupdate'
Offset:              6.282ns (Levels of Logic = 1)
  Source:            T0 (PAD)
  Destination:       IR_15 (LATCH)
  Destination Clock: PCupdate rising

  Data Path: T0 to IR_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            35   0.989   4.345  T0_IBUF (T0_IBUF)
     LDCE_1:GE                 0.948          IR_2
    ----------------------------------------
    Total                      6.282ns (1.937ns logic, 4.345ns route)
                                       (30.8% logic, 69.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'RST'
Offset:              8.635ns (Levels of Logic = 1)
  Source:            PCout_15 (LATCH)
  Destination:       PCout<15> (PAD)
  Source Clock:      RST falling

  Data Path: PCout_15 to PCout<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  PCout_15 (PCout_15)
     OBUF:I->O                 5.652          PCout_15_OBUF (PCout<15>)
    ----------------------------------------
    Total                      8.635ns (7.161ns logic, 1.474ns route)
                                       (82.9% logic, 17.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'T1'
Offset:              8.289ns (Levels of Logic = 1)
  Source:            IRout_15 (FF)
  Destination:       IRout<15> (PAD)
  Source Clock:      T1 rising

  Data Path: IRout_15 to IRout<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   1.372   1.265  IRout_15 (IRout_15)
     OBUF:I->O                 5.652          IRout_15_OBUF (IRout<15>)
    ----------------------------------------
    Total                      8.289ns (7.024ns logic, 1.265ns route)
                                       (84.7% logic, 15.3% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               14.645ns (Levels of Logic = 3)
  Source:            PCupdate (PAD)
  Destination:       PCload (PAD)

  Data Path: PCupdate to PCload
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           67   0.885   6.105  PCupdate_BUFGP (PCupdate_BUFGP)
     LUT3:I2->O            1   0.738   1.265  PCload1 (PCload_OBUF)
     OBUF:I->O                 5.652          PCload_OBUF (PCload)
    ----------------------------------------
    Total                     14.645ns (7.275ns logic, 7.370ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
CPU : 2.14 / 3.03 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 64184 kilobytes