__projnav.log

16位cpu设计VHDL源码

Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Synthesize".


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*                          HDL Compilation                              *
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Compiling vhdl file e:/资料/计算机设计与实践/mycpu16/ALU.vhdl in Library work.
Entity <ALU> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/资料/计算机设计与实践/mycpu16/clock.vhdl in Library work.
Entity <clock> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/资料/计算机设计与实践/mycpu16/code.vhdl in Library work.
Entity <code> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/资料/计算机设计与实践/mycpu16/memory.vhdl in Library work.
Entity <memory> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/资料/计算机设计与实践/mycpu16/visit_memory.vhdl in Library work.
ERROR:HDLParsers:163 - e:/资料/计算机设计与实践/mycpu16/visit_memory.vhdl Line 1. Unexpected symbol read: