wave.vhw

16位cpu设计VHDL源码

-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:56:25 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wave IS
END wave;

ARCHITECTURE testbench_arch OF wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT write_back
		PORT (
			T4 : In  std_logic;
			clk : In  std_logic;
			Rtemp : In  std_logic_vector (7 DOWNTO 0);
			ALUout : In  std_logic_vector (7 DOWNTO 0);
			Addr : In  std_logic_vector (15 DOWNTO 0);
			IRout : In  std_logic_vector (15 DOWNTO 0);
			Rupdate : Out  std_logic;
			PCupdate : Out  std_logic;
			Radd : Out  std_logic_vector (2 DOWNTO 0);
			Rdata : Out  std_logic_vector (7 DOWNTO 0);
			PCnew : Out  std_logic_vector (15 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL T4 : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL Rtemp : std_logic_vector (7 DOWNTO 0);
	SIGNAL ALUout : std_logic_vector (7 DOWNTO 0);
	SIGNAL Addr : std_logic_vector (15 DOWNTO 0);
	SIGNAL IRout : std_logic_vector (15 DOWNTO 0);
	SIGNAL Rupdate : std_logic;
	SIGNAL PCupdate : std_logic;
	SIGNAL Radd : std_logic_vector (2 DOWNTO 0);
	SIGNAL Rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL PCnew : std_logic_vector (15 DOWNTO 0);

BEGIN
	UUT : write_back
	PORT MAP (
		T4 => T4,
		clk => clk,
		Rtemp => Rtemp,
		ALUout => ALUout,
		Addr => Addr,
		IRout => IRout,
		Rupdate => Rupdate,
		PCupdate => PCupdate,
		Radd => Radd,
		Rdata => Rdata,
		PCnew => PCnew
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		clk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Rupdate(
			next_Rupdate : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Rupdate /= next_Rupdate) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Rupdate="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Rupdate);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Rupdate);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_PCupdate(
			next_PCupdate : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (PCupdate /= next_PCupdate) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns PCupdate="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCupdate);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_PCupdate);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_Radd(
			next_Radd : std_logic_vector (2 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Radd /= next_Radd) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Radd="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Radd);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Radd);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_Rdata(
			next_Rdata : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Rdata /= next_Rdata) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Rdata="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Rdata);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Rdata);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_PCnew(
			next_PCnew : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (PCnew /= next_PCnew) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns PCnew="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCnew);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_PCnew);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		T4 <= transport '0';
		Rtemp <= transport std_logic_vector'("00000000"); --0
		ALUout <= transport std_logic_vector'("00000000"); --0
		Addr <= transport std_logic_vector'("0000000000000001"); --1
		IRout <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		T4 <= transport '1';
		ALUout <= transport std_logic_vector'("00010010"); --12
		IRout <= transport std_logic_vector'("0101000000010010"); --5012
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		T4 <= transport '0';
		ALUout <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		T4 <= transport '1';
		ALUout <= transport std_logic_vector'("00010010"); --12
		IRout <= transport std_logic_vector'("0100000100000000"); --4100
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		T4 <= transport '0';
		ALUout <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		T4 <= transport '1';
		ALUout <= transport std_logic_vector'("11111111"); --FF
		IRout <= transport std_logic_vector'("0101011111111111"); --57FF
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		T4 <= transport '0';
		ALUout <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		T4 <= transport '1';
		ALUout <= transport std_logic_vector'("00100100"); --24
		IRout <= transport std_logic_vector'("0000000000000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		T4 <= transport '0';
		ALUout <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		T4 <= transport '1';
		ALUout <= transport std_logic_vector'("00100100"); --24
		IRout <= transport std_logic_vector'("0110000000000000"); --6000
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		T4 <= transport '0';
		ALUout <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		T4 <= transport '1';
		Rtemp <= transport std_logic_vector'("00100100"); --24
		Addr <= transport std_logic_vector'("1111111100000000"); --FF00
		IRout <= transport std_logic_vector'("0111001100000000"); --7300
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		T4 <= transport '0';
		Rtemp <= transport std_logic_vector'("00000000"); --0
		Addr <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		T4 <= transport '1';
		Rtemp <= transport std_logic_vector'("00000000"); --0
		Addr <= transport std_logic_vector'("1111111111011101"); --FFDD
		IRout <= transport std_logic_vector'("1001000011011101"); --90DD
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		T4 <= transport '0';
		Addr <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		IRout <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		T4 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		T4 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		T4 <= transport '1';
		Addr <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		T4 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		T4 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		T4 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2100 ns
		T4 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2200 ns
		T4 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2300 ns
		IRout <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 310 ns; -- Time=2610 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION write_back_cfg OF wave IS
	FOR testbench_arch
	END FOR;
END write_back_cfg;