📄 code.twr
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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml code code.ncd -o
code.twr code.pcf
Design file: code.ncd
Physical constraint file: code.pcf
Device,speed: xcv200,-4 (FINAL 1.123 2003-12-13)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock PCupdate
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRnew<0> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<10> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<11> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<12> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<13> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<14> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<15> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<1> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<2> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<3> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<4> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<5> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<6> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<7> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<8> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
IRnew<9> | 3.200(R)| 0.000(R)|PCupdate_BUFGP | 0.000|
T0 | 9.062(R)| 0.927(R)|PCupdate_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock RST
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
T0 | 10.222(F)| -0.894(F)|RST_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock T1
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
PCnew<0> | 2.976(R)| -0.138(R)|T1_BUFGP | 0.000|
PCnew<10> | 2.963(R)| -0.098(R)|T1_BUFGP | 0.000|
PCnew<11> | 3.022(R)| -0.163(R)|T1_BUFGP | 0.000|
PCnew<12> | 3.628(R)| -0.528(R)|T1_BUFGP | 0.000|
PCnew<13> | 3.715(R)| -0.581(R)|T1_BUFGP | 0.000|
PCnew<14> | 3.531(R)| -0.469(R)|T1_BUFGP | 0.000|
PCnew<15> | 3.292(R)| -0.326(R)|T1_BUFGP | 0.000|
PCnew<1> | 3.662(R)| -0.548(R)|T1_BUFGP | 0.000|
PCnew<2> | 3.296(R)| -0.324(R)|T1_BUFGP | 0.000|
PCnew<3> | 3.215(R)| -0.273(R)|T1_BUFGP | 0.000|
PCnew<4> | 2.707(R)| 0.022(R)|T1_BUFGP | 0.000|
PCnew<5> | 2.792(R)| -0.028(R)|T1_BUFGP | 0.000|
PCnew<6> | 3.711(R)| -0.578(R)|T1_BUFGP | 0.000|
PCnew<7> | 3.003(R)| -0.150(R)|T1_BUFGP | 0.000|
PCnew<8> | 3.517(R)| -0.458(R)|T1_BUFGP | 0.000|
PCnew<9> | 2.991(R)| -0.143(R)|T1_BUFGP | 0.000|
T0 | 12.819(R)| -2.760(R)|T1_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock RST to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
PCout<0> | 12.498(F)|RST_BUFGP | 0.000|
PCout<10> | 11.660(F)|RST_BUFGP | 0.000|
PCout<11> | 12.461(F)|RST_BUFGP | 0.000|
PCout<12> | 11.794(F)|RST_BUFGP | 0.000|
PCout<13> | 12.150(F)|RST_BUFGP | 0.000|
PCout<14> | 12.229(F)|RST_BUFGP | 0.000|
PCout<15> | 12.291(F)|RST_BUFGP | 0.000|
PCout<1> | 11.535(F)|RST_BUFGP | 0.000|
PCout<2> | 12.710(F)|RST_BUFGP | 0.000|
PCout<3> | 12.523(F)|RST_BUFGP | 0.000|
PCout<4> | 11.257(F)|RST_BUFGP | 0.000|
PCout<5> | 11.257(F)|RST_BUFGP | 0.000|
PCout<6> | 11.508(F)|RST_BUFGP | 0.000|
PCout<7> | 11.455(F)|RST_BUFGP | 0.000|
PCout<8> | 11.927(F)|RST_BUFGP | 0.000|
PCout<9> | 12.021(F)|RST_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock T1 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
IRout<0> | 7.911(R)|T1_BUFGP | 0.000|
IRout<10> | 7.934(R)|T1_BUFGP | 0.000|
IRout<11> | 7.912(R)|T1_BUFGP | 0.000|
IRout<12> | 7.912(R)|T1_BUFGP | 0.000|
IRout<13> | 7.911(R)|T1_BUFGP | 0.000|
IRout<14> | 7.980(R)|T1_BUFGP | 0.000|
IRout<15> | 7.911(R)|T1_BUFGP | 0.000|
IRout<1> | 7.911(R)|T1_BUFGP | 0.000|
IRout<2> | 7.911(R)|T1_BUFGP | 0.000|
IRout<3> | 7.911(R)|T1_BUFGP | 0.000|
IRout<4> | 7.911(R)|T1_BUFGP | 0.000|
IRout<5> | 7.911(R)|T1_BUFGP | 0.000|
IRout<6> | 7.912(R)|T1_BUFGP | 0.000|
IRout<7> | 7.912(R)|T1_BUFGP | 0.000|
IRout<8> | 7.980(R)|T1_BUFGP | 0.000|
IRout<9> | 7.911(R)|T1_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock RST
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
PCupdate | | | 6.943| 6.943|
RST | | | | 4.712|
T1 | | | 6.729| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock T1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
PCupdate | 10.259| 10.259| | |
RST | 14.115| 14.115| | |
T1 | 9.360| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
PCupdate |PCload | 11.332|
RST |PCload | 15.115|
T0 |PCload | 13.986|
---------------+---------------+---------+
Analysis completed Sun Nov 11 22:54:14 2007
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Peak Memory Usage: 50 MB
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