cpu_16.syr

16位cpu设计VHDL源码

#      8-bit 8-to-1 multiplexer    : 2
# Tristates                        : 20
#      1-bit tristate buffer       : 16
#      16-bit tristate buffer      : 2
#      3-bit tristate buffer       : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 3
#      16-bit adder                : 1
#      32-bit adder                : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 477
#      GND                         : 1
#      LUT1                        : 48
#      LUT2                        : 20
#      LUT2_L                      : 2
#      LUT3                        : 168
#      LUT3_D                      : 1
#      LUT3_L                      : 18
#      LUT4                        : 54
#      LUT4_D                      : 4
#      LUT4_L                      : 5
#      MUXCY                       : 53
#      MUXF5                       : 32
#      MUXF6                       : 16
#      VCC                         : 1
#      XORCY                       : 54
# FlipFlops/Latches                : 202
#      FDC_1                       : 36
#      FDCE_1                      : 1
#      FDCPE                       : 16
#      FDE                         : 15
#      LD                          : 31
#      LDCE_1                      : 15
#      LDE                         : 72
#      LDE_1                       : 16
# Tri-States                       : 27
#      BUFT                        : 27
# Clock Buffers                    : 6
#      BUFGP                       : 6
# IO Buffers                       : 38
#      IBUF                        : 1
#      IOBUF                       : 15
#      OBUF                        : 5
#      OBUFT                       : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                     176  out of   2352     7%  
 Number of Slice Flip Flops:           202  out of   4704     4%  
 Number of 4 input LUTs:               320  out of   4704     6%  
 Number of bonded IOBs:                 38  out of    170    22%  
 Number of TBUFs:                       27  out of   2352     1%  
 Number of GCLKs:                        6  out of      4   150% (*) 

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
PCload_C(u4_PCload1:O)             | NONE(*)(u6_IRnew_7)    | 23    |
clk                                | BUFGP+BUFGP            | 37    |
u2__n0079(u2__n007978:O)           | NONE(*)(u2_ALUout_temp_6_1)| 16    |
u2__n0011(u2__n00111:O)            | NONE(*)(u2_regsters_7_5)| 8     |
u2__n0015(u2__n00151:O)            | NONE(*)(u2_regsters_3_3)| 8     |
u2__n0016(u2__n00161:O)            | NONE(*)(u2_regsters_2_4)| 8     |
u2__n0072(u2__n00721:O)            | NONE(*)(u2_regsters_0_0)| 8     |
u2__n0014(u2__n00141:O)            | NONE(*)(u2_regsters_4_7)| 8     |
u2__n0017(u2__n00171:O)            | NONE(*)(u2_regsters_1_5)| 8     |
u2__n0013(u2__n00131:O)            | NONE(*)(u2_regsters_5_2)| 8     |
u2__n0012(u2__n00121:O)            | NONE(*)(u2_regsters_6_0)| 8     |
u3_T_1:Q                           | NONE                   | 31    |
RST                                | IBUF                   | 16    |
u7_PCupdate52_1(u7_PCupdate52_1:O) | NONE(*)(u4_IR_14)      | 15    |
-----------------------------------+------------------------+-------+
(*) These 11 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.219ns (Maximum Frequency: 75.649MHz)
   Minimum input arrival time before clock: 10.045ns
   Maximum output required time after clock: 28.551ns
   Maximum combinational path delay: 20.735ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_PCload1:O'
Delay:               4.486ns (Levels of Logic = 1)
  Source:            u6_data_5 (LATCH)
  Destination:       u6_data_5 (LATCH)
  Source Clock:      u4_PCload1:O rising
  Destination Clock: u4_PCload1:O rising

  Data Path: u6_data_5 to u6_data_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            2   1.509   1.474  u6_data_5 (u6_data_5)
     LUT3:I2->O            1   0.738   0.000  u6_Mmux__n0006_Result<5>1 (u6__n0006<5>)
     LDE_1:D                   0.765          u6_data_5
    ----------------------------------------
    Total                      4.486ns (3.012ns logic, 1.474ns route)
                                       (67.1% logic, 32.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               13.219ns (Levels of Logic = 5)
  Source:            u3_num_12 (FF)
  Destination:       u3_T_1 (FF)
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: u3_num_12 to u3_T_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.372   1.474  u3_num_12 (u3_num_12)
     LUT4:I0->O            1   0.738   1.265  u3_Ker721799 (CHOICE912)
     LUT4:I1->O            3   0.738   1.628  u3_Ker7217149 (CHOICE929)
     LUT4_D:I3->O          4   0.738   1.760  u3_Ker7217165 (u3_N7219)
     LUT3_D:I0->O          1   0.738   1.265  u3_Ker71901 (u3_N7192)
     LUT4_L:I1->LO         1   0.738   0.000  u3__n0002<1>1 (u3__n0002<1>)
     FDC_1:D                   0.765          u3_T_1
    ----------------------------------------
    Total                     13.219ns (5.827ns logic, 7.392ns route)
                                       (44.1% logic, 55.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u3_T_1:Q'
Delay:               10.386ns (Levels of Logic = 2)
  Source:            u4_IRout_12 (FF)
  Destination:       u4_IRout_15 (FF)
  Source Clock:      u3_T_1:Q rising
  Destination Clock: u3_T_1:Q rising

  Data Path: u4_IRout_12 to u4_IRout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             20   1.372   3.520  u4_IRout_12 (u4_IRout_12)
     LUT4_D:I0->LO         1   0.738   0.100  u7_PCupdate52 (N16713)
     LUT3:I2->O           15   0.738   2.970  u4__n00071 (u4__n0007)
     FDE:CE                    0.948          u4_IRout_0
    ----------------------------------------
    Total                     10.386ns (3.796ns logic, 6.590ns route)
                                       (36.5% logic, 63.5% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'RST'
Delay:               4.486ns (Levels of Logic = 1)
  Source:            u4_PCout_15 (LATCH)
  Destination:       u4_PCout_15 (LATCH)
  Source Clock:      RST falling
  Destination Clock: RST falling

  Data Path: u4_PCout_15 to u4_PCout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  u4_PCout_15 (u4_PCout_15)
     LUT3:I1->O            1   0.738   0.000  u4_Mmux__n0006_Result<15>1 (u4__n0006<15>)
     LDE:D                     0.765          u4_PCout_15
    ----------------------------------------
    Total                      4.486ns (3.012ns logic, 1.474ns route)
                                       (67.1% logic, 32.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u3_T_1:Q'
Offset:              10.045ns (Levels of Logic = 2)
  Source:            RST (PAD)
  Destination:       u4_IRout_15 (FF)
  Destination Clock: u3_T_1:Q rising

  Data Path: RST to u4_IRout_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            36   0.989   4.400  RST_IBUF (RST_IBUF)
     LUT3:I1->O           15   0.738   2.970  u4__n00071 (u4__n0007)
     FDE:CE                    0.948          u4_IRout_0
    ----------------------------------------
    Total                     10.045ns (2.675ns logic, 7.370ns route)
                                       (26.6% logic, 73.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u2__n007978:O'
Offset:              28.551ns (Levels of Logic = 6)
  Source:            u2_ALUout_temp_0 (LATCH)
  Destination:       Abus<15> (PAD)
  Source Clock:      u2__n007978:O falling

  Data Path: u2_ALUout_temp_0 to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               2   1.509   1.474  u2_ALUout_temp_0 (u2_ALUout_temp_0)
     LUT4:I0->O            1   0.738   1.265  u7_PCupdate12 (CHOICE862)
     LUT2:I0->O            3   0.738   1.628  u7_PCupdate26 (CHOICE870)
     LUT4:I1->O           49   0.738   5.115  u7_PCupdate52_1 (u7_PCupdate52_1)
     LUT3:I1->O           42   0.738   4.730  u4_PCload1 (PCload_C)
     LUT4:I0->O           18   0.738   3.300  u6_nMREQ1 (nMREQ_OBUF)
     OBUFT:T->O                5.840          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     28.551ns (11.039ns logic, 17.512ns route)
                                       (38.7% logic, 61.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              24.716ns (Levels of Logic = 4)
  Source:            u3_T_4 (FF)
  Destination:       Abus<15> (PAD)
  Source Clock:      clk falling

  Data Path: u3_T_4 to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q           7   1.372   2.145  u3_T_4 (u3_T_4)
     LUT4:I2->O           49   0.738   5.115  u7_PCupdate52_1 (u7_PCupdate52_1)
     LUT3:I1->O           42   0.738   4.730  u4_PCload1 (PCload_C)
     LUT4:I0->O           18   0.738   3.300  u6_nMREQ1 (nMREQ_OBUF)
     OBUFT:T->O                5.840          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     24.716ns (9.426ns logic, 15.290ns route)
                                       (38.1% logic, 61.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u3_T_1:Q'
Offset:              26.091ns (Levels of Logic = 4)
  Source:            u4_IRout_12 (FF)
  Destination:       Abus<15> (PAD)
  Source Clock:      u3_T_1:Q rising

  Data Path: u4_IRout_12 to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             20   1.372   3.520  u4_IRout_12 (u4_IRout_12)
     LUT4:I0->O           49   0.738   5.115  u7_PCupdate52_1 (u7_PCupdate52_1)
     LUT3:I1->O           42   0.738   4.730  u4_PCload1 (PCload_C)
     LUT4:I0->O           18   0.738   3.300  u6_nMREQ1 (nMREQ_OBUF)
     OBUFT:T->O                5.840          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     26.091ns (9.426ns logic, 16.665ns route)
                                       (36.1% logic, 63.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u2__n00111:O'
Offset:              10.924ns (Levels of Logic = 2)
  Source:            u2_regsters_7_7 (LATCH)
  Destination:       Abus<15> (PAD)
  Source Clock:      u2__n00111:O falling

  Data Path: u2_regsters_7_7 to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              4   1.509   1.760  u2_regsters_7_7 (u2_regsters_7_7)
     LUT3:I1->O            1   0.738   1.265  u6_Mmux__n0007_Result<15>1 (Abus_15_OBUFT)
     OBUFT:I->O                5.652          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     10.924ns (7.899ns logic, 3.025ns route)
                                       (72.3% logic, 27.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'RST'
Offset:              10.638ns (Levels of Logic = 2)
  Source:            u4_PCout_15 (LATCH)
  Destination:       Abus<15> (PAD)
  Source Clock:      RST falling

  Data Path: u4_PCout_15 to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  u4_PCout_15 (u4_PCout_15)
     LUT3:I2->O            1   0.738   1.265  u6_Mmux__n0007_Result<15>1 (Abus_15_OBUFT)
     OBUFT:I->O                5.652          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     10.638ns (7.899ns logic, 2.739ns route)
                                       (74.3% logic, 25.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               20.735ns (Levels of Logic = 4)
  Source:            RST (PAD)
  Destination:       Abus<15> (PAD)

  Data Path: RST to Abus<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            36   0.989   4.400  RST_IBUF (RST_IBUF)
     LUT3:I0->O           42   0.738   4.730  u4_PCload1 (PCload_C)
     LUT4:I0->O           18   0.738   3.300  u6_nMREQ1 (nMREQ_OBUF)
     OBUFT:T->O                5.840          Abus_15_OBUFT (Abus<15>)
    ----------------------------------------
    Total                     20.735ns (8.305ns logic, 12.430ns route)
                                       (40.1% logic, 59.9% route)

=========================================================================
CPU : 6.05 / 6.95 s | Elapsed : 6.00 / 7.00 s
 
--> 

Total memory usage is 71352 kilobytes