cpu_16.syr

16位cpu设计VHDL源码

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: cpu_16.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : cpu_16.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : cpu_16
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : cpu_16
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : cpu_16.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl in Library work.
Architecture behavioral of Entity alu is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/clock.vhdl in Library work.
Architecture behavioral of Entity clock is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/code.vhdl in Library work.
Architecture behavioral of Entity code is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/memory.vhdl in Library work.
Architecture behavioral of Entity memory is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/visit_memory.vhdl in Library work.
Architecture behavioral of Entity visit_memory is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/write_back.vhdl in Library work.
Architecture behavioral of Entity write_back is up to date.
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/CPU_16.vhdl in Library work.
Entity <cpu_16> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cpu_16> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/CPU_16.vhdl line 113: Generating a Black Box for component <bufgp>.
Entity <cpu_16> analyzed. Unit <cpu_16> generated.

Analyzing Entity <alu> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 35: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 36: The following signals are missing in the process sensitivity list:
   regsters<$n0001>, regsters<$n0000>, regsters.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 78: The following signals are missing in the process sensitivity list:
   Rdata.
Entity <alu> analyzed. Unit <alu> generated.

Analyzing Entity <clock> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/clock.vhdl line 22: Generating a Black Box for component <bufgp>.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <code> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/code.vhdl line 29: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/code.vhdl line 30: The following signals are missing in the process sensitivity list:
   PCnew, PC, IRnew.
Entity <code> analyzed. Unit <code> generated.

Analyzing Entity <memory> (Architecture <behavioral>).
Entity <memory> analyzed. Unit <memory> generated.

Analyzing Entity <visit_memory> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/visit_memory.vhdl line 34: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/visit_memory.vhdl line 35: The following signals are missing in the process sensitivity list:
   PCout, Addr, ALUout.
Entity <visit_memory> analyzed. Unit <visit_memory> generated.

Analyzing Entity <write_back> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/write_back.vhdl line 29: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/write_back.vhdl line 30: The following signals are missing in the process sensitivity list:
   Addr, ALUout, Rtemp.
Entity <write_back> analyzed. Unit <write_back> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <write_back>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/write_back.vhdl.
WARNING:Xst:647 - Input <IRout<11>> is never used.
WARNING:Xst:647 - Input <IRout<7:0>> is never used.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
    Found 8-bit tristate buffer for signal <Rdata>.
    Found 3-bit tristate buffer for signal <Radd>.
    Found 16-bit tristate buffer for signal <PCnew>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   8 Multiplexer(s).
	inferred  27 Tristate(s).
Unit <write_back> synthesized.


Synthesizing Unit <visit_memory>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/visit_memory.vhdl.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
WARNING:Xst:737 - Found 16-bit latch for signal <IRnew>.
WARNING:Xst:737 - Found 8-bit latch for signal <data>.
    Found 16-bit tristate buffer for signal <Dbus>.
    Found 16-bit tristate buffer for signal <Abus>.
    Found 24 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  24 Multiplexer(s).
	inferred  32 Tristate(s).
Unit <visit_memory> synthesized.


Synthesizing Unit <memory>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/memory.vhdl.
Unit <memory> synthesized.


Synthesizing Unit <code>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/code.vhdl.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
WARNING:Xst:737 - Found 16-bit latch for signal <IR>.
WARNING:Xst:737 - Found 16-bit latch for signal <PCout>.
    Found 16-bit register for signal <IRout>.
    Found 16-bit up counter for signal <PC>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <code> synthesized.


Synthesizing Unit <clock>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/clock.vhdl.
    Found 5-bit register for signal <T>.
    Found 32-bit adder for signal <$n0001> created at line 41.
    Found 32-bit register for signal <num>.
    Summary:
	inferred  37 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <clock> synthesized.


Synthesizing Unit <alu>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl.
WARNING:Xst:647 - Input <IRout<11>> is never used.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_7>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_6>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_5>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_4>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_3>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_2>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_1>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_0>.
WARNING:Xst:737 - Found 8-bit latch for signal <ALUout_temp>.
    Found 8-bit addsub for signal <$n0033>.
    Found 8-bit 8-to-1 multiplexer for signal <temp_A>.
    Found 8-bit 8-to-1 multiplexer for signal <temp_B>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred  18 Multiplexer(s).
Unit <alu> synthesized.


Synthesizing Unit <cpu_16>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/CPU_16.vhdl.
Unit <cpu_16> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 8-bit addsub                      : 1
 32-bit adder                      : 1
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 3
 5-bit register                    : 1
 32-bit register                   : 1
 16-bit register                   : 1
# Latches                          : 13
 8-bit latch                       : 10
 16-bit latch                      : 3
# Multiplexers                     : 8
 1-bit 2-to-1 multiplexer          : 2
 8-bit 8-to-1 multiplexer          : 2
 16-bit 2-to-1 multiplexer         : 2
 8-bit 2-to-1 multiplexer          : 2
# Tristates                        : 20
 1-bit tristate buffer             : 16
 16-bit tristate buffer            : 2
 8-bit tristate buffer             : 1
 3-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <IRout_11> is unconnected in block <u4>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <cpu_16> ...

Optimizing unit <clock> ...

Optimizing unit <write_back> ...

Optimizing unit <alu> ...

Optimizing unit <code> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u6_IRnew_11> is unconnected in block <cpu_16>.
WARNING:Xst:1291 - FF/Latch <u4_IRout_11> is unconnected in block <cpu_16>.
WARNING:Xst:1291 - FF/Latch <u4_IR_11> is unconnected in block <cpu_16>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cpu_16, actual ratio is 9.
Latch u2_ALUout_temp_0 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_1 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_2 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_3 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_4 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_5 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_6 has been replicated 1 time(s) to handle iob=true attribute.
Latch u2_ALUout_temp_7 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cpu_16.ngr
Top Level Output File Name         : cpu_16
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 39

Macro Statistics :
# Registers                        : 3
#      16-bit register             : 1
#      32-bit register             : 1
#      5-bit register              : 1
# Multiplexers                     : 9
#      2-to-1 multiplexer          : 7