mycpu16.npl

16位cpu设计VHDL源码

JDF G
// Created by Project Navigator ver 1.0
PROJECT MyCPU16
DESIGN mycpu16
DEVFAM virtex
DEVFAMTIME 0
DEVICE xcv200
DEVICETIME 0
DEVPKG pq240
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE code.vhdl
SOURCE CPU_16.vhdl
SOURCE ALU.vhdl
SOURCE write_back.vhdl
SOURCE clock.vhdl
SOURCE visit_memory.vhdl
SOURCE memory.vhdl
STIMULUS cpu_16_wave.tbw
STIMULUS cw.tbw
STIMULUS wave.tbw
STIMULUS ALU_WAVE.tbw
STIMULUS code_wave.tbw
STIMULUS memory_wave.tbw
STIMULUS visit_memory_wave.tbw
[STATUS-ALL]
alu.ngcFile=WARNINGS,1194833727
clock.ncdFile=WARNINGS,1194791923
clock.ngcFile=WARNINGS,1194791898
cpu_16.ngcFile=WARNINGS,1194833934
visit_memory.ngcFile=WARNINGS,1194833764
write_back.ncdFile=WARNINGS,1194833789
write_back.ngcFile=WARNINGS,1194833777
write_back.ngdFile=WARNINGS,1194833781
[STRATEGY-LIST]
Normal=True