📄 visit_memory.mrp
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| Abus<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Abus<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Addr<0> | IOB | INPUT | LVTTL | | | | | || Addr<1> | IOB | INPUT | LVTTL | | | | | || Addr<2> | IOB | INPUT | LVTTL | | | | | || Addr<3> | IOB | INPUT | LVTTL | | | | | || Addr<4> | IOB | INPUT | LVTTL | | | | | || Addr<5> | IOB | INPUT | LVTTL | | | | | || Addr<6> | IOB | INPUT | LVTTL | | | | | || Addr<7> | IOB | INPUT | LVTTL | | | | | || Addr<8> | IOB | INPUT | LVTTL | | | | | || Addr<9> | IOB | INPUT | LVTTL | | | | | || Addr<10> | IOB | INPUT | LVTTL | | | | | || Addr<11> | IOB | INPUT | LVTTL | | | | | || Addr<12> | IOB | INPUT | LVTTL | | | | | || Addr<13> | IOB | INPUT | LVTTL | | | | | || Addr<14> | IOB | INPUT | LVTTL | | | | | || Addr<15> | IOB | INPUT | LVTTL | | | | | || Dbus<0> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<1> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<2> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<3> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<4> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<5> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<6> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<7> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || Dbus<8> | IOB | BIDIR | LVTTL | | | | | || Dbus<9> | IOB | BIDIR | LVTTL | | | | | || Dbus<10> | IOB | BIDIR | LVTTL | | | | | || Dbus<11> | IOB | BIDIR | LVTTL | | | | | || Dbus<12> | IOB | BIDIR | LVTTL | | | | | || Dbus<13> | IOB | BIDIR | LVTTL | | | | | || Dbus<14> | IOB | BIDIR | LVTTL | | | | | || Dbus<15> | IOB | BIDIR | LVTTL | | | | | || IRnew<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || IRnew<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTLATCH | | || PCout<0> | IOB | INPUT | LVTTL | | | | | || PCout<1> | IOB | INPUT | LVTTL | | | | | || PCout<2> | IOB | INPUT | LVTTL | | | | | || PCout<3> | IOB | INPUT | LVTTL | | | | | || PCout<4> | IOB | INPUT | LVTTL | | | | | || PCout<5> | IOB | INPUT | LVTTL | | | | | || PCout<6> | IOB | INPUT | LVTTL | | | | | || PCout<7> | IOB | INPUT | LVTTL | | | | | || PCout<8> | IOB | INPUT | LVTTL | | | | | || PCout<9> | IOB | INPUT | LVTTL | | | | | || PCout<10> | IOB | INPUT | LVTTL | | | | | || PCout<11> | IOB | INPUT | LVTTL | | | | | || PCout<12> | IOB | INPUT | LVTTL | | | | | || PCout<13> | IOB | INPUT | LVTTL | | | | | || PCout<14> | IOB | INPUT | LVTTL | | | | | || PCout<15> | IOB | INPUT | LVTTL | | | | | || data<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nBHE | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nBLE | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nMRD | IOB | INPUT | LVTTL | | | | | || nMREQ | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nMWR | IOB | INPUT | LVTTL | | | | | || nRD | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nWR | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 104Number of Equivalent Gates for Design = 354Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 16IOB Latches not driven by LUTs = 16IOB Latches = 16IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 103Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 04 input LUTs = 27Slice Latches not driven by LUTs = 0Slice Latches = 8Slice Flip Flops not driven by LUTs = 0Slice Flip Flops = 0Slices = 14Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 0Number of LUT signals with 1 load = 25NGM Average fanout of LUT = 1.93NGM Maximum fanout of LUT = 18NGM Average fanin for LUT = 2.9630Number of LUT symbols = 27Number of IPAD symbols = 43Number of IBUF symbols = 58Number of BIPAD symbols = 16
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