hdllib.ref

16位cpu设计VHDL源码

EN clock NULL C:/Xilinx/bin/MyCPU16/clock.vhdl sub00/vhpl04
EN visit_memory NULL C:/Xilinx/bin/MyCPU16/visit_memory.vhdl sub00/vhpl10
AR alu behavioral C:/Xilinx/bin/MyCPU16/ALU.vhdl sub00/vhpl03
EN cpu_16 NULL C:/Xilinx/bin/MyCPU16/CPU_16.vhdl sub00/vhpl00
AR visit_memory behavioral C:/Xilinx/bin/MyCPU16/visit_memory.vhdl sub00/vhpl11
AR code behavioral C:/Xilinx/bin/MyCPU16/code.vhdl sub00/vhpl07
AR clock behavioral C:/Xilinx/bin/MyCPU16/clock.vhdl sub00/vhpl05
EN memory NULL C:/Xilinx/bin/MyCPU16/memory.vhdl sub00/vhpl08
EN code NULL C:/Xilinx/bin/MyCPU16/code.vhdl sub00/vhpl06
AR memory behavioral C:/Xilinx/bin/MyCPU16/memory.vhdl sub00/vhpl09
EN write_back NULL C:/Xilinx/bin/MyCPU16/write_back.vhdl sub00/vhpl12
AR write_back behavioral C:/Xilinx/bin/MyCPU16/write_back.vhdl sub00/vhpl13
AR cpu_16 behavioral C:/Xilinx/bin/MyCPU16/CPU_16.vhdl sub00/vhpl01
EN alu NULL C:/Xilinx/bin/MyCPU16/ALU.vhdl sub00/vhpl02