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📄 code.mrp

📁 16位cpu设计VHDL源码
💻 MRP
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| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| PCupdate                           | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || RST                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || T1                                 | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || IRnew<0>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<1>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<2>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<3>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<4>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<5>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<6>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<7>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<8>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<9>                           | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<10>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<11>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<12>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<13>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<14>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRnew<15>                          | IOB     | INPUT     | LVTTL       |          |      | INLATCH  |          | IFD   || IRout<0>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<1>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<2>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<3>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<4>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<5>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<6>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<7>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<8>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<9>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<10>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<11>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<12>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<13>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<14>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || IRout<15>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || PCload                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCnew<0>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<1>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<2>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<3>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<4>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<5>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<6>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<7>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<8>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<9>                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<10>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<11>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<12>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<13>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<14>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCnew<15>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       || PCout<0>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<1>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<2>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<3>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<4>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<5>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<6>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<7>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<8>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<9>                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<10>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<11>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<12>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<13>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<14>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PCout<15>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || T0                                 | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 69Number of Equivalent Gates for Design = 908Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 3GCLKs = 3Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 32IOB Latches not driven by LUTs = 16IOB Latches = 16IOB Flip Flops not driven by LUTs = 16IOB Flip Flops = 16Unbonded IOBs = 0Bonded IOBs = 66Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 154 input LUTs = 67Slice Latches not driven by LUTs = 0Slice Latches = 16Slice Flip Flops not driven by LUTs = 0Slice Flip Flops = 16Slices = 41Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 0Number of LUT signals with 1 load = 66NGM Average fanout of LUT = 1.22NGM Maximum fanout of LUT = 16NGM Average fanin for LUT = 2.7313Number of LUT symbols = 67Number of IPAD symbols = 36Number of IBUF symbols = 33

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