code.mrp

16位cpu设计VHDL源码

Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'code'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv200-pq240-4 -cm
area -pr b -k 4 -c 100 -tx off -o code_map.ncd code.ngd code.pcf 
Target Device  : xv200
Target Package : pq240
Target Speed   : -4
Mapper Version : virtex -- $Revision: 1.16.8.1 $
Mapped Date    : Sun Nov 11 22:54:09 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Total Number Slice Registers:      32 out of  4,704    1%
    Number used as Flip Flops:                     16
    Number used as Latches:                        16
  Number of 4 input LUTs:            67 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                          41 out of  2,352    1%
    Number of Slices containing only related logic:     41 out of     41  100%
    Number of Slices containing unrelated logic:         0 out of     41    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           82 out of  4,704    1%
      Number used as logic:                        67
      Number used as a route-thru:                 15
   Number of bonded IOBs:            66 out of    166   39%
      IOB Flip Flops:                              16
      IOB Latches:                                 16
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                3 out of      4   75%

Total equivalent gate count for design:  908
Additional JTAG gate count for IOBs:  3,312
Peak Memory Usage:  64 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFG symbol
   "PCupdate_BUFGP/BUFG" (output signal=PCupdate_BUFGP) has a mix of clock and
   non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
   Pin I2 of _n00071
   Pin I2 of PCload1
   Pin CE of PCout_15
   Pin CE of PCout_14
   Pin CE of PCout_0
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFG symbol
   "RST_BUFGP/BUFG" (output signal=RST_BUFGP) has a mix of clock and non-clock
   loads. Some of the non-clock loads are (maximum of 5 listed):
   Pin I1 of _n00071
   Pin I1 of PCload1
   Pin CLR of IR_15
   Pin CLR of IR_14
   Pin CLR of IR_0

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------
   3 block(s) removed
   2 block(s) optimized away
   3 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "u1/IBUFG" is sourceless and has been removed.
 Sourceless block "u1/BUFG" (CKBUF) removed.
  The signal "u1/O" is sourceless and has been removed.

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "clk" is unused and has been removed.
 Unused block "clk" (PAD) removed.
Unused block "u1/IBUFG" (CKBUF) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

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