memory_wave.ant

16位cpu设计VHDL源码

-- C:\XILINX\BIN\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:08 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY memory_wave IS
END memory_wave;

ARCHITECTURE testbench_arch OF memory_wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\xilinx\bin\mycpu16\memory_wave.ano";
	COMPONENT memory
		PORT (
			T3 : In  std_logic;
			MRD_C : In  std_logic;
			MWR_C : In  std_logic;
			Rtemp : Out  std_logic_vector (7 DOWNTO 0);
			data : In  std_logic_vector (7 DOWNTO 0);
			nMRD : Out  std_logic;
			nMWR : Out  std_logic
		);
	END COMPONENT;

	SIGNAL T3 : std_logic;
	SIGNAL MRD_C : std_logic;
	SIGNAL MWR_C : std_logic;
	SIGNAL Rtemp : std_logic_vector (7 DOWNTO 0);
	SIGNAL data : std_logic_vector (7 DOWNTO 0);
	SIGNAL nMRD : std_logic;
	SIGNAL nMWR : std_logic;

BEGIN
	UUT : memory
	PORT MAP (
		T3 => T3,
		MRD_C => MRD_C,
		MWR_C => MWR_C,
		Rtemp => Rtemp,
		data => data,
		nMRD => nMRD,
		nMWR => nMWR
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_Rtemp(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Rtemp,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Rtemp);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nMRD(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nMRD,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMRD);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nMWR(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nMWR,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMWR);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_Rtemp(TX_TIME);
		ANNOTATE_nMRD(TX_TIME);
		ANNOTATE_nMWR(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		T3 <= transport '0';
		MRD_C <= transport '0';
		MWR_C <= transport '0';
		data <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		T3 <= transport '1';
		MRD_C <= transport '1';
		data <= transport std_logic_vector'("10101011"); --AB
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		T3 <= transport '0';
		MRD_C <= transport '0';
		data <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		T3 <= transport '1';
		MWR_C <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		T3 <= transport '0';
		MWR_C <= transport '0';
		-- --------------------
		WAIT FOR 300 ns; -- Time=700 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION memory_cfg OF memory_wave IS
	FOR testbench_arch
	END FOR;
END memory_cfg;