alu.par

16位cpu设计VHDL源码

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

song::  Sun Nov 11 22:48:40 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 alu_map.ncd alu.ncd
alu.pcf 


Constraints file: alu.pcf

Loading device database for application Par from file "alu_map.ncd".
   "alu" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-12-13.


Device utilization summary:

   Number of External IOBs            55 out of 166    33%
      Number of LOCed External IOBs    0 out of 55      0%

   Number of SLICEs                   98 out of 2352    4%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989897) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
..
Phase 5.8 (Checksum:a16b6f) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file alu.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 686 unrouted;       REAL time: 0 secs 

Phase 2: 661 unrouted;       REAL time: 2 secs 

Phase 3: 185 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|            _n0011          |   Local  |   12   |  1.428     |  3.621      |
+----------------------------+----------+--------+------------+-------------+
|            _n0079          |   Local  |    8   |  0.233     |  4.123      |
+----------------------------+----------+--------+------------+-------------+
|            _n0017          |   Local  |    4   |  0.077     |  3.802      |
+----------------------------+----------+--------+------------+-------------+
|            _n0072          |   Local  |    5   |  2.106     |  3.591      |
+----------------------------+----------+--------+------------+-------------+
|            _n0016          |   Local  |    4   |  0.666     |  1.755      |
+----------------------------+----------+--------+------------+-------------+
|            _n0015          |   Local  |    4   |  0.026     |  3.403      |
+----------------------------+----------+--------+------------+-------------+
|            _n0014          |   Local  |    4   |  2.491     |  3.726      |
+----------------------------+----------+--------+------------+-------------+
|            _n0013          |   Local  |    4   |  0.025     |  3.593      |
+----------------------------+----------+--------+------------+-------------+
|            _n0012          |   Local  |    4   |  0.013     |  3.580      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 379


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.752
   The MAXIMUM PIN DELAY IS:                               6.419
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   5.179

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
          64         153         181         161         127           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file alu.ncd.


PAR done.