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📄 alu.twr

📁 16位cpu设计VHDL源码
💻 TWR
📖 第 1 页 / 共 3 页
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            |   -0.238(F)|    5.061(F)|_n0015            |   0.000|
            |    0.810(F)|    3.289(F)|_n0014            |   0.000|
            |   -1.087(F)|    6.219(F)|_n0013            |   0.000|
            |   -0.993(F)|    6.156(F)|_n0012            |   0.000|
Rdata<6>    |   -0.467(R)|    4.772(R)|_n0072            |   0.000|
            |   -0.058(F)|    5.884(F)|_n0011            |   0.000|
            |    0.306(F)|    4.326(F)|_n0017            |   0.000|
            |    0.373(F)|    4.123(F)|_n0016            |   0.000|
            |   -0.274(F)|    5.089(F)|_n0015            |   0.000|
            |   -0.576(F)|    5.563(F)|_n0014            |   0.000|
            |   -1.053(F)|    6.202(F)|_n0013            |   0.000|
            |   -1.012(F)|    6.174(F)|_n0012            |   0.000|
Rdata<7>    |   -1.108(R)|    5.153(R)|_n0072            |   0.000|
            |   -0.058(F)|    5.768(F)|_n0011            |   0.000|
            |    0.483(F)|    4.216(F)|_n0017            |   0.000|
            |    0.498(F)|    4.044(F)|_n0016            |   0.000|
            |   -0.057(F)|    4.955(F)|_n0015            |   0.000|
            |    0.193(F)|    5.098(F)|_n0014            |   0.000|
            |   -0.916(F)|    6.116(F)|_n0013            |   0.000|
            |   -0.316(F)|    5.752(F)|_n0012            |   0.000|
Rupdate     |    1.059(R)|    5.047(R)|_n0072            |   0.000|
            |    0.344(F)|    6.185(F)|_n0011            |   0.000|
            |    1.177(F)|    4.472(F)|_n0017            |   0.000|
            |    2.256(F)|    3.893(F)|_n0016            |   0.000|
            |    1.173(F)|    4.816(F)|_n0015            |   0.000|
            |    2.055(F)|    5.202(F)|_n0014            |   0.000|
            |    0.440(F)|    6.621(F)|_n0013            |   0.000|
            |    0.494(F)|    6.623(F)|_n0012            |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock Radd<2>
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
Rdata<0>    |    1.126(R)|    2.387(R)|_n0072            |   0.000|
            |    0.121(F)|    6.161(F)|_n0011            |   0.000|
            |   -1.735(F)|    5.982(F)|_n0017            |   0.000|
            |    0.735(F)|    3.227(F)|_n0016            |   0.000|
            |   -0.613(F)|    5.252(F)|_n0015            |   0.000|
            |   -0.996(F)|    4.445(F)|_n0014            |   0.000|
            |   -0.770(F)|    5.469(F)|_n0013            |   0.000|
            |   -1.087(F)|    5.766(F)|_n0012            |   0.000|
Rdata<1>    |    1.126(R)|    2.387(R)|_n0072            |   0.000|
            |   -0.685(F)|    5.392(F)|_n0011            |   0.000|
            |   -2.052(F)|    6.168(F)|_n0017            |   0.000|
            |    1.309(F)|    2.879(F)|_n0016            |   0.000|
            |   -0.132(F)|    4.959(F)|_n0015            |   0.000|
            |    1.001(F)|    3.243(F)|_n0014            |   0.000|
            |   -0.294(F)|    5.180(F)|_n0013            |   0.000|
            |   -0.476(F)|    5.396(F)|_n0012            |   0.000|
Rdata<2>    |   -1.408(R)|    5.542(R)|_n0072            |   0.000|
            |    0.485(F)|    5.317(F)|_n0011            |   0.000|
            |   -0.722(F)|    5.331(F)|_n0017            |   0.000|
            |   -0.269(F)|    4.056(F)|_n0016            |   0.000|
            |   -0.951(F)|    5.466(F)|_n0015            |   0.000|
            |   -1.290(F)|    6.025(F)|_n0014            |   0.000|
            |   -1.098(F)|    5.680(F)|_n0013            |   0.000|
            |   -1.554(F)|    6.051(F)|_n0012            |   0.000|
Rdata<3>    |   -1.550(R)|    5.623(R)|_n0072            |   0.000|
            |    0.491(F)|    5.295(F)|_n0011            |   0.000|
            |   -0.412(F)|    5.142(F)|_n0017            |   0.000|
            |    0.460(F)|    3.615(F)|_n0016            |   0.000|
            |   -0.424(F)|    5.146(F)|_n0015            |   0.000|
            |   -0.919(F)|    5.798(F)|_n0014            |   0.000|
            |   -0.591(F)|    5.372(F)|_n0013            |   0.000|
            |   -0.961(F)|    5.691(F)|_n0012            |   0.000|
Rdata<4>    |   -1.326(R)|    5.508(R)|_n0072            |   0.000|
            |   -0.171(F)|    4.914(F)|_n0011            |   0.000|
            |   -1.503(F)|    5.798(F)|_n0017            |   0.000|
            |    1.593(F)|    2.552(F)|_n0016            |   0.000|
            |   -0.135(F)|    4.978(F)|_n0015            |   0.000|
            |    1.469(F)|    2.924(F)|_n0014            |   0.000|
            |   -0.087(F)|    5.072(F)|_n0013            |   0.000|
            |   -0.256(F)|    5.272(F)|_n0012            |   0.000|
Rdata<5>    |   -1.351(R)|    5.519(R)|_n0072            |   0.000|
            |    0.491(F)|    5.013(F)|_n0011            |   0.000|
            |   -1.413(F)|    5.740(F)|_n0017            |   0.000|
            |    1.313(F)|    2.716(F)|_n0016            |   0.000|
            |   -0.208(F)|    5.018(F)|_n0015            |   0.000|
            |    0.777(F)|    3.336(F)|_n0014            |   0.000|
            |   -0.422(F)|    5.269(F)|_n0013            |   0.000|
            |   -0.456(F)|    5.388(F)|_n0012            |   0.000|
Rdata<6>    |   -0.724(R)|    5.140(R)|_n0072            |   0.000|
            |    0.491(F)|    5.099(F)|_n0011            |   0.000|
            |   -0.164(F)|    4.997(F)|_n0017            |   0.000|
            |    0.996(F)|    3.233(F)|_n0016            |   0.000|
            |   -0.244(F)|    5.046(F)|_n0015            |   0.000|
            |   -0.608(F)|    5.610(F)|_n0014            |   0.000|
            |   -0.388(F)|    5.252(F)|_n0013            |   0.000|
            |   -0.474(F)|    5.406(F)|_n0012            |   0.000|
Rdata<7>    |   -1.365(R)|    5.521(R)|_n0072            |   0.000|
            |    0.491(F)|    4.983(F)|_n0011            |   0.000|
            |    0.013(F)|    4.887(F)|_n0017            |   0.000|
            |    1.121(F)|    3.154(F)|_n0016            |   0.000|
            |   -0.027(F)|    4.912(F)|_n0015            |   0.000|
            |    0.161(F)|    5.145(F)|_n0014            |   0.000|
            |   -0.251(F)|    5.166(F)|_n0013            |   0.000|
            |    0.222(F)|    4.984(F)|_n0012            |   0.000|
Rupdate     |    0.801(R)|    5.415(R)|_n0072            |   0.000|
            |    0.893(F)|    5.400(F)|_n0011            |   0.000|
            |    0.707(F)|    5.143(F)|_n0017            |   0.000|
            |    2.879(F)|    3.003(F)|_n0016            |   0.000|
            |    1.203(F)|    4.773(F)|_n0015            |   0.000|
            |    2.022(F)|    5.249(F)|_n0014            |   0.000|
            |    1.105(F)|    5.671(F)|_n0013            |   0.000|
            |    1.031(F)|    5.855(F)|_n0012            |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock T2
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
IRout<0>    |   13.265(F)|    7.416(F)|_n0079            |   0.000|
IRout<1>    |   13.382(F)|    7.336(F)|_n0079            |   0.000|
IRout<2>    |   13.688(F)|    7.827(F)|_n0079            |   0.000|
IRout<3>    |    0.966(F)|    7.918(F)|_n0079            |   0.000|
IRout<4>    |    1.979(F)|    7.294(F)|_n0079            |   0.000|
IRout<5>    |    2.394(F)|    7.119(F)|_n0079            |   0.000|
IRout<6>    |    1.033(F)|    7.986(F)|_n0079            |   0.000|
IRout<7>    |    0.550(F)|    8.226(F)|_n0079            |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock T3
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
IRout<0>    |   13.684(F)|    4.728(F)|_n0079            |   0.000|
IRout<1>    |   13.801(F)|    4.648(F)|_n0079            |   0.000|
IRout<2>    |   14.107(F)|    5.139(F)|_n0079            |   0.000|
IRout<3>    |    1.385(F)|    5.230(F)|_n0079            |   0.000|
IRout<4>    |    2.399(F)|    4.606(F)|_n0079            |   0.000|
IRout<5>    |    2.813(F)|    4.431(F)|_n0079            |   0.000|
IRout<6>    |    1.452(F)|    5.298(F)|_n0079            |   0.000|
IRout<7>    |    0.969(F)|    5.538(F)|_n0079            |   0.000|
------------+------------+------------+------------------+--------+

Clock IRout<10> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   23.930(F)|_n0079            |   0.000|
ALUout<1>   |   23.930(F)|_n0079            |   0.000|
ALUout<2>   |   23.912(F)|_n0079            |   0.000|
ALUout<3>   |   23.724(F)|_n0079            |   0.000|
ALUout<4>   |   23.697(F)|_n0079            |   0.000|
ALUout<5>   |   23.825(F)|_n0079            |   0.000|
ALUout<6>   |   23.912(F)|_n0079            |   0.000|
ALUout<7>   |   23.825(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<12> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   17.242(F)|_n0079            |   0.000|
ALUout<1>   |   17.242(F)|_n0079            |   0.000|
ALUout<2>   |   17.224(F)|_n0079            |   0.000|
ALUout<3>   |   17.036(F)|_n0079            |   0.000|
ALUout<4>   |   17.009(F)|_n0079            |   0.000|
ALUout<5>   |   17.137(F)|_n0079            |   0.000|
ALUout<6>   |   17.224(F)|_n0079            |   0.000|
ALUout<7>   |   17.137(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<13> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   20.066(F)|_n0079            |   0.000|
ALUout<1>   |   20.066(F)|_n0079            |   0.000|
ALUout<2>   |   20.048(F)|_n0079            |   0.000|
ALUout<3>   |   19.860(F)|_n0079            |   0.000|
ALUout<4>   |   19.833(F)|_n0079            |   0.000|
ALUout<5>   |   19.961(F)|_n0079            |   0.000|
ALUout<6>   |   20.048(F)|_n0079            |   0.000|
ALUout<7>   |   19.961(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<14> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   19.092(F)|_n0079            |   0.000|
ALUout<1>   |   19.092(F)|_n0079            |   0.000|
ALUout<2>   |   19.074(F)|_n0079            |   0.000|
ALUout<3>   |   18.886(F)|_n0079            |   0.000|
ALUout<4>   |   18.859(F)|_n0079            |   0.000|
ALUout<5>   |   18.987(F)|_n0079            |   0.000|
ALUout<6>   |   19.074(F)|_n0079            |   0.000|
ALUout<7>   |   18.987(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<15> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   20.850(F)|_n0079            |   0.000|
ALUout<1>   |   20.850(F)|_n0079            |   0.000|
ALUout<2>   |   20.832(F)|_n0079            |   0.000|
ALUout<3>   |   20.644(F)|_n0079            |   0.000|
ALUout<4>   |   20.617(F)|_n0079            |   0.000|
ALUout<5>   |   20.745(F)|_n0079            |   0.000|
ALUout<6>   |   20.832(F)|_n0079            |   0.000|
ALUout<7>   |   20.745(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<8> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   22.358(F)|_n0079            |   0.000|
ALUout<1>   |   22.358(F)|_n0079            |   0.000|
ALUout<2>   |   22.340(F)|_n0079            |   0.000|
ALUout<3>   |   22.152(F)|_n0079            |   0.000|
ALUout<4>   |   22.125(F)|_n0079            |   0.000|
ALUout<5>   |   22.253(F)|_n0079            |   0.000|
ALUout<6>   |   22.340(F)|_n0079            |   0.000|
ALUout<7>   |   22.253(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock IRout<9> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ALUout<0>   |   22.602(F)|_n0079            |   0.000|
ALUout<1>   |   22.602(F)|_n0079            |   0.000|
ALUout<2>   |   22.584(F)|_n0079            |   0.000|
ALUout<3>   |   22.396(F)|_n0079            |   0.000|
ALUout<4>   |   22.369(F)|_n0079            |   0.000|
ALUout<5>   |   22.497(F)|_n0079            |   0.000|
ALUout<6>   |   22.584(F)|_n0079            |   0.000|
ALUout<7>   |   22.497(F)|_n0079            |   0.000|
------------+------------+------------------+--------+

Clock Radd<0> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Addr<10>    |   14.011(F)|_n0011            |   0.000|
Addr<11>    |   13.968(F)|_n0011            |   0.000|
Addr<12>    |   14.997(F)|_n0011            |   0.000|
Addr<13>    |   13.995(F)|_n0011            |   0.000|
Addr<14>    |   14.456(F)|_n0011            |   0.000|
Addr<15>    |   15.401(F)|_n0011            |   0.000|
Addr<8>     |   12.351(F)|_n0011            |   0.000|
Addr<9>     |   12.755(F)|_n0011            |   0.000|
------------+------------+------------------+--------+

Clock Radd<1> to Pad
------------+------------+------------------+--------+

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