📄 alu.twr
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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml alu alu.ncd -o alu.twr
alu.pcf
Design file: alu.ncd
Physical constraint file: alu.pcf
Device,speed: xcv200,-4 (FINAL 1.123 2003-12-13)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock IRout<10>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 10.737(F)| 12.675(F)|_n0079 | 0.000|
IRout<1> | 10.854(F)| 12.595(F)|_n0079 | 0.000|
IRout<2> | 11.160(F)| 13.086(F)|_n0079 | 0.000|
IRout<3> | -1.562(F)| 13.177(F)|_n0079 | 0.000|
IRout<4> | -0.548(F)| 12.553(F)|_n0079 | 0.000|
IRout<5> | -0.134(F)| 12.378(F)|_n0079 | 0.000|
IRout<6> | -1.495(F)| 13.245(F)|_n0079 | 0.000|
IRout<7> | -1.978(F)| 13.485(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<12>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 12.803(F)| 5.987(F)|_n0079 | 0.000|
IRout<1> | 12.920(F)| 5.907(F)|_n0079 | 0.000|
IRout<2> | 13.226(F)| 6.398(F)|_n0079 | 0.000|
IRout<3> | 0.504(F)| 6.489(F)|_n0079 | 0.000|
IRout<4> | 1.517(F)| 5.865(F)|_n0079 | 0.000|
IRout<5> | 1.932(F)| 5.690(F)|_n0079 | 0.000|
IRout<6> | 0.571(F)| 6.557(F)|_n0079 | 0.000|
IRout<7> | 0.088(F)| 6.797(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<13>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 10.826(F)| 8.811(F)|_n0079 | 0.000|
IRout<1> | 10.943(F)| 8.731(F)|_n0079 | 0.000|
IRout<2> | 11.249(F)| 9.222(F)|_n0079 | 0.000|
IRout<3> | -1.473(F)| 9.313(F)|_n0079 | 0.000|
IRout<4> | -0.459(F)| 8.689(F)|_n0079 | 0.000|
IRout<5> | -0.045(F)| 8.514(F)|_n0079 | 0.000|
IRout<6> | -1.406(F)| 9.381(F)|_n0079 | 0.000|
IRout<7> | -1.889(F)| 9.621(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<14>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 11.508(F)| 7.837(F)|_n0079 | 0.000|
IRout<1> | 11.625(F)| 7.757(F)|_n0079 | 0.000|
IRout<2> | 11.931(F)| 8.248(F)|_n0079 | 0.000|
IRout<3> | -0.792(F)| 8.339(F)|_n0079 | 0.000|
IRout<4> | 0.222(F)| 7.715(F)|_n0079 | 0.000|
IRout<5> | 0.637(F)| 7.540(F)|_n0079 | 0.000|
IRout<6> | -0.724(F)| 8.407(F)|_n0079 | 0.000|
IRout<7> | -1.207(F)| 8.647(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<15>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 12.823(F)| 9.595(F)|_n0079 | 0.000|
IRout<1> | 12.940(F)| 9.515(F)|_n0079 | 0.000|
IRout<2> | 13.246(F)| 10.006(F)|_n0079 | 0.000|
IRout<3> | 0.523(F)| 10.097(F)|_n0079 | 0.000|
IRout<4> | 1.537(F)| 9.473(F)|_n0079 | 0.000|
IRout<5> | 1.951(F)| 9.298(F)|_n0079 | 0.000|
IRout<6> | 0.591(F)| 10.165(F)|_n0079 | 0.000|
IRout<7> | 0.107(F)| 10.405(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<8>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 10.841(F)| 11.103(F)|_n0079 | 0.000|
IRout<1> | 10.958(F)| 11.023(F)|_n0079 | 0.000|
IRout<2> | 11.264(F)| 11.514(F)|_n0079 | 0.000|
IRout<3> | -1.458(F)| 11.605(F)|_n0079 | 0.000|
IRout<4> | -0.444(F)| 10.981(F)|_n0079 | 0.000|
IRout<5> | -0.030(F)| 10.806(F)|_n0079 | 0.000|
IRout<6> | -1.391(F)| 11.673(F)|_n0079 | 0.000|
IRout<7> | -1.874(F)| 11.913(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock IRout<9>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
IRout<0> | 11.418(F)| 11.347(F)|_n0079 | 0.000|
IRout<1> | 11.535(F)| 11.267(F)|_n0079 | 0.000|
IRout<2> | 11.841(F)| 11.758(F)|_n0079 | 0.000|
IRout<3> | -0.881(F)| 11.849(F)|_n0079 | 0.000|
IRout<4> | 0.133(F)| 11.225(F)|_n0079 | 0.000|
IRout<5> | 0.547(F)| 11.050(F)|_n0079 | 0.000|
IRout<6> | -0.814(F)| 11.917(F)|_n0079 | 0.000|
IRout<7> | -1.297(F)| 12.157(F)|_n0079 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock Radd<0>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
Rdata<0> | 1.385(R)| 2.018(R)|_n0072 | 0.000|
| -0.015(F)| 6.356(F)|_n0011 | 0.000|
| -1.654(F)| 5.867(F)|_n0017 | 0.000|
| 0.436(F)| 3.654(F)|_n0016 | 0.000|
| -0.234(F)| 4.710(F)|_n0015 | 0.000|
| -1.159(F)| 4.677(F)|_n0014 | 0.000|
| -0.894(F)| 5.645(F)|_n0013 | 0.000|
| -1.063(F)| 5.731(F)|_n0012 | 0.000|
Rdata<1> | 1.385(R)| 2.018(R)|_n0072 | 0.000|
| -0.822(F)| 5.587(F)|_n0011 | 0.000|
| -1.971(F)| 6.053(F)|_n0017 | 0.000|
| 1.010(F)| 3.306(F)|_n0016 | 0.000|
| 0.247(F)| 4.417(F)|_n0015 | 0.000|
| 0.838(F)| 3.475(F)|_n0014 | 0.000|
| -0.418(F)| 5.356(F)|_n0013 | 0.000|
| -0.452(F)| 5.361(F)|_n0012 | 0.000|
Rdata<2> | -1.149(R)| 5.173(R)|_n0072 | 0.000|
| 0.349(F)| 5.512(F)|_n0011 | 0.000|
| -0.641(F)| 5.216(F)|_n0017 | 0.000|
| -0.568(F)| 4.483(F)|_n0016 | 0.000|
| -0.572(F)| 4.924(F)|_n0015 | 0.000|
| -1.453(F)| 6.257(F)|_n0014 | 0.000|
| -1.221(F)| 5.856(F)|_n0013 | 0.000|
| -1.529(F)| 6.016(F)|_n0012 | 0.000|
Rdata<3> | -1.291(R)| 5.254(R)|_n0072 | 0.000|
| 0.355(F)| 5.490(F)|_n0011 | 0.000|
| -0.331(F)| 5.027(F)|_n0017 | 0.000|
| 0.161(F)| 4.042(F)|_n0016 | 0.000|
| -0.045(F)| 4.604(F)|_n0015 | 0.000|
| -1.082(F)| 6.030(F)|_n0014 | 0.000|
| -0.714(F)| 5.548(F)|_n0013 | 0.000|
| -0.936(F)| 5.656(F)|_n0012 | 0.000|
Rdata<4> | -1.068(R)| 5.139(R)|_n0072 | 0.000|
| -0.307(F)| 5.109(F)|_n0011 | 0.000|
| -1.422(F)| 5.683(F)|_n0017 | 0.000|
| 1.294(F)| 2.979(F)|_n0016 | 0.000|
| 0.244(F)| 4.436(F)|_n0015 | 0.000|
| 1.307(F)| 3.156(F)|_n0014 | 0.000|
| -0.210(F)| 5.248(F)|_n0013 | 0.000|
| -0.231(F)| 5.237(F)|_n0012 | 0.000|
Rdata<5> | -1.093(R)| 5.150(R)|_n0072 | 0.000|
| 0.355(F)| 5.208(F)|_n0011 | 0.000|
| -1.332(F)| 5.625(F)|_n0017 | 0.000|
| 1.014(F)| 3.143(F)|_n0016 | 0.000|
| 0.171(F)| 4.476(F)|_n0015 | 0.000|
| 0.615(F)| 3.568(F)|_n0014 | 0.000|
| -0.545(F)| 5.445(F)|_n0013 | 0.000|
| -0.431(F)| 5.353(F)|_n0012 | 0.000|
Rdata<6> | -0.466(R)| 4.771(R)|_n0072 | 0.000|
| 0.355(F)| 5.294(F)|_n0011 | 0.000|
| -0.083(F)| 4.882(F)|_n0017 | 0.000|
| 0.697(F)| 3.660(F)|_n0016 | 0.000|
| 0.135(F)| 4.504(F)|_n0015 | 0.000|
| -0.771(F)| 5.842(F)|_n0014 | 0.000|
| -0.512(F)| 5.428(F)|_n0013 | 0.000|
| -0.450(F)| 5.371(F)|_n0012 | 0.000|
Rdata<7> | -1.107(R)| 5.152(R)|_n0072 | 0.000|
| 0.355(F)| 5.178(F)|_n0011 | 0.000|
| 0.094(F)| 4.772(F)|_n0017 | 0.000|
| 0.822(F)| 3.581(F)|_n0016 | 0.000|
| 0.352(F)| 4.370(F)|_n0015 | 0.000|
| -0.002(F)| 5.377(F)|_n0014 | 0.000|
| -0.375(F)| 5.342(F)|_n0013 | 0.000|
| 0.246(F)| 4.949(F)|_n0012 | 0.000|
Rupdate | 1.059(R)| 5.046(R)|_n0072 | 0.000|
| 0.757(F)| 5.595(F)|_n0011 | 0.000|
| 0.788(F)| 5.028(F)|_n0017 | 0.000|
| 2.580(F)| 3.430(F)|_n0016 | 0.000|
| 1.582(F)| 4.231(F)|_n0015 | 0.000|
| 1.859(F)| 5.481(F)|_n0014 | 0.000|
| 0.982(F)| 5.847(F)|_n0013 | 0.000|
| 1.056(F)| 5.820(F)|_n0012 | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock Radd<1>
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
Rdata<0> | 1.384(R)| 2.019(R)|_n0072 | 0.000|
| -0.428(F)| 6.946(F)|_n0011 | 0.000|
| -1.265(F)| 5.311(F)|_n0017 | 0.000|
| 0.112(F)| 4.117(F)|_n0016 | 0.000|
| -0.643(F)| 5.295(F)|_n0015 | 0.000|
| -0.963(F)| 4.398(F)|_n0014 | 0.000|
| -1.435(F)| 6.419(F)|_n0013 | 0.000|
| -1.625(F)| 6.534(F)|_n0012 | 0.000|
Rdata<1> | 1.384(R)| 2.019(R)|_n0072 | 0.000|
| -1.235(F)| 6.177(F)|_n0011 | 0.000|
| -1.582(F)| 5.497(F)|_n0017 | 0.000|
| 0.686(F)| 3.769(F)|_n0016 | 0.000|
| -0.162(F)| 5.002(F)|_n0015 | 0.000|
| 1.034(F)| 3.196(F)|_n0014 | 0.000|
| -0.959(F)| 6.130(F)|_n0013 | 0.000|
| -1.014(F)| 6.164(F)|_n0012 | 0.000|
Rdata<2> | -1.150(R)| 5.174(R)|_n0072 | 0.000|
| -0.064(F)| 6.102(F)|_n0011 | 0.000|
| -0.252(F)| 4.660(F)|_n0017 | 0.000|
| -0.892(F)| 4.946(F)|_n0016 | 0.000|
| -0.981(F)| 5.509(F)|_n0015 | 0.000|
| -1.258(F)| 5.978(F)|_n0014 | 0.000|
| -1.763(F)| 6.630(F)|_n0013 | 0.000|
| -2.091(F)| 6.819(F)|_n0012 | 0.000|
Rdata<3> | -1.292(R)| 5.255(R)|_n0072 | 0.000|
| -0.058(F)| 6.080(F)|_n0011 | 0.000|
| 0.058(F)| 4.471(F)|_n0017 | 0.000|
| -0.163(F)| 4.505(F)|_n0016 | 0.000|
| -0.454(F)| 5.189(F)|_n0015 | 0.000|
| -0.887(F)| 5.751(F)|_n0014 | 0.000|
| -1.256(F)| 6.322(F)|_n0013 | 0.000|
| -1.498(F)| 6.459(F)|_n0012 | 0.000|
Rdata<4> | -1.068(R)| 5.140(R)|_n0072 | 0.000|
| -0.720(F)| 5.699(F)|_n0011 | 0.000|
| -1.033(F)| 5.127(F)|_n0017 | 0.000|
| 0.970(F)| 3.442(F)|_n0016 | 0.000|
| -0.165(F)| 5.021(F)|_n0015 | 0.000|
| 1.502(F)| 2.877(F)|_n0014 | 0.000|
| -0.752(F)| 6.022(F)|_n0013 | 0.000|
| -0.793(F)| 6.040(F)|_n0012 | 0.000|
Rdata<5> | -1.093(R)| 5.151(R)|_n0072 | 0.000|
| -0.058(F)| 5.798(F)|_n0011 | 0.000|
| -0.943(F)| 5.069(F)|_n0017 | 0.000|
| 0.690(F)| 3.606(F)|_n0016 | 0.000|
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