alu.syr

16位cpu设计VHDL源码

_n0012(_n00121:O)                  | NONE(*)(regsters_6_1)  | 8     |
-----------------------------------+------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 20.032ns
   Maximum output required time after clock: 8.426ns
   Maximum combinational path delay: 14.684ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n007978:O'
Offset:              20.032ns (Levels of Logic = 17)
  Source:            IRout<8> (PAD)
  Destination:       ALUout_temp_7 (LATCH)
  Destination Clock: _n007978:O falling

  Data Path: IRout<8> to ALUout_temp_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            32   0.989   4.180  IRout_8_IBUF (IRout_8_IBUF)
     LUT3:I0->O            1   0.738   0.000  Mmux_temp_A_inst_lut3_81 (Mmux_temp_A__net0)
     MUXF5:I0->O           1   0.562   0.000  Mmux_temp_A_inst_mux_f5_0 (Mmux_temp_A__net2)
     MUXF6:I0->O           5   0.412   1.914  Mmux_temp_A_inst_mux_f6_0 (temp_A<0>)
     LUT3:I0->O            1   0.738   0.000  Maddsub__n0033_inst_lut3_01 (Maddsub__n0033_inst_lut3_0)
     MUXCY:S->O            1   0.842   0.000  Maddsub__n0033_inst_cy_0 (Maddsub__n0033_inst_cy_0)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0033_inst_cy_1 (Maddsub__n0033_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0033_inst_cy_2 (Maddsub__n0033_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0033_inst_cy_3 (Maddsub__n0033_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0033_inst_cy_4 (Maddsub__n0033_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0033_inst_cy_5 (Maddsub__n0033_inst_cy_5)
     MUXCY:CI->O           0   0.057   0.000  Maddsub__n0033_inst_cy_6 (Maddsub__n0033_inst_cy_6)
     XORCY:CI->O           1   0.538   1.265  Maddsub__n0033_inst_sum_7 (_n0033<7>)
     LUT4:I3->O            1   0.738   1.265  _n0021<7>13 (CHOICE620)
     LUT3:I1->O            1   0.738   1.265  _n0021<7>29 (CHOICE625)
     LUT4:I1->O            1   0.738   1.265  _n0021<7>81_SW0 (N7747)
     LUT4:I2->O            1   0.738   0.000  _n0021<7>81 (_n0021<7>)
     LD:D                      0.765          ALUout_temp_7
    ----------------------------------------
    Total                     20.032ns (8.878ns logic, 11.154ns route)
                                       (44.3% logic, 55.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00111:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_7_5 (LATCH)
  Destination Clock: _n00111:O falling

  Data Path: Rupdate to regsters_7_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_7_1
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00151:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_3_5 (LATCH)
  Destination Clock: _n00151:O falling

  Data Path: Rupdate to regsters_3_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_3_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00161:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_2_5 (LATCH)
  Destination Clock: _n00161:O falling

  Data Path: Rupdate to regsters_2_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_2_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00721:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_0_5 (LATCH)
  Destination Clock: _n00721:O rising

  Data Path: Rupdate to regsters_0_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE_1:GE                  0.948          regsters_0_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00141:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_4_5 (LATCH)
  Destination Clock: _n00141:O falling

  Data Path: Rupdate to regsters_4_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_4_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00171:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_1_5 (LATCH)
  Destination Clock: _n00171:O falling

  Data Path: Rupdate to regsters_1_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_1_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00131:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_5_5 (LATCH)
  Destination Clock: _n00131:O falling

  Data Path: Rupdate to regsters_5_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_5_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00121:O'
Offset:              8.317ns (Levels of Logic = 1)
  Source:            Rupdate (PAD)
  Destination:       regsters_6_5 (LATCH)
  Destination Clock: _n00121:O falling

  Data Path: Rupdate to regsters_6_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            72   0.989   6.380  Rupdate_IBUF (Rupdate_IBUF)
     LDE:GE                    0.948          regsters_6_2
    ----------------------------------------
    Total                      8.317ns (1.937ns logic, 6.380ns route)
                                       (23.3% logic, 76.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00111:O'
Offset:              8.426ns (Levels of Logic = 1)
  Source:            regsters_7_7_1 (LATCH)
  Destination:       Addr<15> (PAD)
  Source Clock:      _n00111:O falling

  Data Path: regsters_7_7_1 to Addr<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              1   1.509   1.265  regsters_7_7_1 (regsters_7_7_1)
     OBUF:I->O                 5.652          Addr_15_OBUF (Addr<15>)
    ----------------------------------------
    Total                      8.426ns (7.161ns logic, 1.265ns route)
                                       (85.0% logic, 15.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n007978:O'
Offset:              8.426ns (Levels of Logic = 1)
  Source:            ALUout_temp_7 (LATCH)
  Destination:       ALUout<7> (PAD)
  Source Clock:      _n007978:O falling

  Data Path: ALUout_temp_7 to ALUout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.509   1.265  ALUout_temp_7 (ALUout_temp_7)
     OBUF:I->O                 5.652          ALUout_7_OBUF (ALUout<7>)
    ----------------------------------------
    Total                      8.426ns (7.161ns logic, 1.265ns route)
                                       (85.0% logic, 15.0% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               14.684ns (Levels of Logic = 4)
  Source:            IRout<14> (PAD)
  Destination:       MWR_C (PAD)

  Data Path: IRout<14> to MWR_C
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            15   0.989   2.970  IRout_14_IBUF (IRout_14_IBUF)
     LUT3:I0->O            1   0.738   1.265  Ker2937_SW1 (N7751)
     LUT4:I2->O            9   0.738   2.332  Ker2937 (MWR_C_OBUF)
     OBUF:I->O                 5.652          MWR_C_OBUF (MWR_C)
    ----------------------------------------
    Total                     14.684ns (8.117ns logic, 6.567ns route)
                                       (55.3% logic, 44.7% route)

=========================================================================
CPU : 4.41 / 5.30 s | Elapsed : 5.00 / 6.00 s
 
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Total memory usage is 67256 kilobytes