alu.syr

16位cpu设计VHDL源码

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: alu.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : alu.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : alu
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : alu
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : alu.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl in Library work.
Architecture behavioral of Entity alu is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 35: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 36: The following signals are missing in the process sensitivity list:
   regsters<$n0001>, regsters<$n0000>, regsters.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl line 78: The following signals are missing in the process sensitivity list:
   Rdata.
Entity <alu> analyzed. Unit <alu> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alu>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl.
WARNING:Xst:647 - Input <IRout<11>> is never used.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_7>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_6>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_5>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_4>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_3>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_2>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_1>.
WARNING:Xst:737 - Found 8-bit latch for signal <regsters_0>.
WARNING:Xst:737 - Found 8-bit latch for signal <ALUout_temp>.
    Found 8-bit addsub for signal <$n0033>.
    Found 8-bit 8-to-1 multiplexer for signal <temp_A>.
    Found 8-bit 8-to-1 multiplexer for signal <temp_B>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred  18 Multiplexer(s).
Unit <alu> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit addsub                      : 1
# Latches                          : 9
 8-bit latch                       : 9
# Multiplexers                     : 4
 1-bit 2-to-1 multiplexer          : 2
 8-bit 8-to-1 multiplexer          : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <alu> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block alu, actual ratio is 3.
Latch regsters_7_7 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_6 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_5 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_4 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_3 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_2 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_1 has been replicated 1 time(s) to handle iob=true attribute.
Latch regsters_7_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : alu.ngr
Top Level Output File Name         : alu
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 57

Macro Statistics :
# Multiplexers                     : 4
#      2-to-1 multiplexer          : 2
#      8-bit 8-to-1 multiplexer    : 2
# Adders/Subtractors               : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 197
#      LUT2                        : 1
#      LUT3                        : 94
#      LUT4                        : 39
#      MUXCY                       : 7
#      MUXF5                       : 32
#      MUXF6                       : 16
#      XORCY                       : 8
# FlipFlops/Latches                : 80
#      LD                          : 8
#      LDE                         : 64
#      LDE_1                       : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 55
#      IBUF                        : 29
#      OBUF                        : 26
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                      82  out of   2352     3%  
 Number of Slice Flip Flops:            80  out of   4704     1%  
 Number of 4 input LUTs:               134  out of   4704     2%  
 Number of bonded IOBs:                 55  out of    170    32%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0079(_n007978:O)                 | NONE(*)(ALUout_temp_1) | 8     |
_n0011(_n00111:O)                  | NONE(*)(regsters_7_2)  | 16    |
_n0015(_n00151:O)                  | NONE(*)(regsters_3_2)  | 8     |
_n0016(_n00161:O)                  | NONE(*)(regsters_2_1)  | 8     |
_n0072(_n00721:O)                  | NONE(*)(regsters_0_3)  | 8     |
_n0014(_n00141:O)                  | NONE(*)(regsters_4_3)  | 8     |
_n0017(_n00171:O)                  | NONE(*)(regsters_1_4)  | 8     |
_n0013(_n00131:O)                  | NONE(*)(regsters_5_4)  | 8     |