📄 code_wave.vhw
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-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:40:12 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY UNISIM;USE UNISIM.VCOMPONENTS.ALL;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY code_wave IS
END code_wave;
ARCHITECTURE testbench_arch OF code_wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT code
PORT (
RST : In std_logic;
T0 : In std_logic;
T1 : In std_logic;
clk : In std_logic;
PCupdate : In std_logic;
PCnew : In std_logic_vector (15 DOWNTO 0);
IRnew : In std_logic_vector (15 DOWNTO 0);
PCload : Out std_logic;
IRout : Out std_logic_vector (15 DOWNTO 0);
PCout : Out std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
SIGNAL RST : std_logic;
SIGNAL T0 : std_logic;
SIGNAL T1 : std_logic;
SIGNAL clk : std_logic;
SIGNAL PCupdate : std_logic;
SIGNAL PCnew : std_logic_vector (15 DOWNTO 0);
SIGNAL IRnew : std_logic_vector (15 DOWNTO 0);
SIGNAL PCload : std_logic;
SIGNAL IRout : std_logic_vector (15 DOWNTO 0);
SIGNAL PCout : std_logic_vector (15 DOWNTO 0);
BEGIN
UUT : code
PORT MAP (
RST => RST,
T0 => T0,
T1 => T1,
clk => clk,
PCupdate => PCupdate,
PCnew => PCnew,
IRnew => IRnew,
PCload => PCload,
IRout => IRout,
PCout => PCout
);
PROCESS -- clock process for clk,
BEGIN
CLOCK_LOOP : LOOP
clk <= transport '0';
WAIT FOR 10 ns;
clk <= transport '1';
WAIT FOR 10 ns;
WAIT FOR 40 ns;
clk <= transport '0';
WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for clk
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_PCload(
next_PCload : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (PCload /= next_PCload) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns PCload="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCload);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_PCload);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_IRout(
next_IRout : std_logic_vector (15 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (IRout /= next_IRout) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns IRout="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRout);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_IRout);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_PCout(
next_PCout : std_logic_vector (15 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (PCout /= next_PCout) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns PCout="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, PCout);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_PCout);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
RST <= transport '0';
T0 <= transport '0';
T1 <= transport '0';
PCupdate <= transport '0';
PCnew <= transport std_logic_vector'("0000000000000000"); --0
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
RST <= transport '1';
T0 <= transport '1';
IRnew <= transport std_logic_vector'("0101000010101011"); --50AB
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
T0 <= transport '0';
T1 <= transport '1';
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
T0 <= transport '1';
T1 <= transport '0';
IRnew <= transport std_logic_vector'("0101011111111111"); --57FF
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
T0 <= transport '0';
T1 <= transport '1';
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=500 ns
T0 <= transport '1';
T1 <= transport '0';
IRnew <= transport std_logic_vector'("0001011100000000"); --1700
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
T0 <= transport '0';
T1 <= transport '1';
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=700 ns
T0 <= transport '1';
T1 <= transport '0';
PCupdate <= transport '1';
PCnew <= transport std_logic_vector'("1111111100000001"); --FF01
IRnew <= transport std_logic_vector'("0110000000000000"); --6000
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
T0 <= transport '0';
T1 <= transport '1';
PCupdate <= transport '0';
PCnew <= transport std_logic_vector'("0000000000000000"); --0
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=900 ns
T0 <= transport '1';
T1 <= transport '0';
IRnew <= transport std_logic_vector'("0100000100000000"); --4100
-- --------------------
WAIT FOR 100 ns; -- Time=1000 ns
T0 <= transport '0';
T1 <= transport '1';
IRnew <= transport std_logic_vector'("0000000000000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=1100 ns
T0 <= transport '1';
T1 <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=1200 ns
T0 <= transport '0';
T1 <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=1300 ns
T0 <= transport '1';
T1 <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=1400 ns
T0 <= transport '0';
T1 <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=1500 ns
T1 <= transport '0';
-- --------------------
WAIT FOR 420 ns; -- Time=1920 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION code_cfg OF code_wave IS
FOR testbench_arch
END FOR;
END code_cfg;
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