📄 write_back.mrp
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Release 6.2i Map G.28Xilinx Mapping Report File for Design 'write_back'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv200-pq240-4 -cm
area -pr b -k 4 -c 100 -tx off -o write_back_map.ncd write_back.ngd
write_back.pcf Target Device : xv200Target Package : pq240Target Speed : -4Mapper Version : virtex -- $Revision: 1.16.8.1 $Mapped Date : Mon Nov 12 10:16:27 2007Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 17 out of 4,704 1%Logic Distribution: Number of occupied Slices: 9 out of 2,352 1% Number of Slices containing only related logic: 9 out of 9 100% Number of Slices containing unrelated logic: 0 out of 9 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 17 out of 4,704 1% Number of bonded IOBs: 69 out of 166 41%Total equivalent gate count for design: 183Additional JTAG gate count for IOBs: 3,312Peak Memory Usage: 63 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 3 block(s) removed 3 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).The signal "u1/IBUFG" is sourceless and has been removed. Sourceless block "u1/BUFG" (CKBUF) removed. The signal "u1/O" is sourceless and has been removed.The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logicThe signal "clk" is unused and has been removed. Unused block "clk" (PAD) removed.Unused block "u1/IBUFG" (CKBUF) removed.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| ALUout<0> | IOB | INPUT | LVTTL | | | | | || ALUout<1> | IOB | INPUT | LVTTL | | | | | || ALUout<2> | IOB | INPUT | LVTTL | | | | | || ALUout<3> | IOB | INPUT | LVTTL | | | | | || ALUout<4> | IOB | INPUT | LVTTL | | | | | || ALUout<5> | IOB | INPUT | LVTTL | | | | | || ALUout<6> | IOB | INPUT | LVTTL | | | | | || ALUout<7> | IOB | INPUT | LVTTL | | | | | || Addr<0> | IOB | INPUT | LVTTL | | | | | || Addr<1> | IOB | INPUT | LVTTL | | | | | || Addr<2> | IOB | INPUT | LVTTL | | | | | || Addr<3> | IOB | INPUT | LVTTL | | | | | || Addr<4> | IOB | INPUT | LVTTL | | | | | || Addr<5> | IOB | INPUT | LVTTL | | | | | || Addr<6> | IOB | INPUT | LVTTL | | | | | || Addr<7> | IOB | INPUT | LVTTL | | | | | || Addr<8> | IOB | INPUT | LVTTL | | | | | || Addr<9> | IOB | INPUT | LVTTL | | | | | || Addr<10> | IOB | INPUT | LVTTL | | | | | || Addr<11> | IOB | INPUT | LVTTL | | | | | || Addr<12> | IOB | INPUT | LVTTL | | | | | || Addr<13> | IOB | INPUT | LVTTL | | | | | || Addr<14> | IOB | INPUT | LVTTL | | | | | || Addr<15> | IOB | INPUT | LVTTL | | | | | || IRout<8> | IOB | INPUT | LVTTL | | | | | || IRout<9> | IOB | INPUT | LVTTL | | | | | || IRout<10> | IOB | INPUT | LVTTL | | | | | || IRout<12> | IOB | INPUT | LVTTL | | | | | || IRout<13> | IOB | INPUT | LVTTL | | | | | || IRout<14> | IOB | INPUT | LVTTL | | | | | || IRout<15> | IOB | INPUT | LVTTL | | | | | || PCnew<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCnew<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PCupdate | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Radd<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Radd<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Radd<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rdata<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Rtemp<0> | IOB | INPUT | LVTTL | | | | | || Rtemp<1> | IOB | INPUT | LVTTL | | | | | || Rtemp<2> | IOB | INPUT | LVTTL | | | | | || Rtemp<3> | IOB | INPUT | LVTTL | | | | | || Rtemp<4> | IOB | INPUT | LVTTL | | | | | || Rtemp<5> | IOB | INPUT | LVTTL | | | | | || Rtemp<6> | IOB | INPUT | LVTTL | | | | | || Rtemp<7> | IOB | INPUT | LVTTL | | | | | || Rupdate | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || T4 | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 69Number of Equivalent Gates for Design = 183Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 0GCLKs = 0Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 69Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 04 input LUTs = 17Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 0Slice Flip Flops = 0Slices = 9Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 1Number of LUT signals with 1 load = 13NGM Average fanout of LUT = 2.94NGM Maximum fanout of LUT = 16NGM Average fanin for LUT = 3.0588Number of LUT symbols = 17Number of IPAD symbols = 40Number of IBUF symbols = 40⌨️ 快捷键说明
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