memory.twr

来自「16位cpu设计VHDL源码」· TWR 代码 · 共 52 行

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml memory memory.ncd -o
memory.twr memory.pcf


Design file:              memory.ncd
Physical constraint file: memory.pcf
Device,speed:             xcv200,-4 (FINAL 1.123 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
MRD_C          |nMRD           |    9.883|
MWR_C          |nMRD           |    9.142|
MWR_C          |nMWR           |    8.442|
T3             |nMRD           |    9.136|
T3             |nMWR           |    8.410|
data<0>        |Rtemp<0>       |    7.984|
data<1>        |Rtemp<1>       |    7.537|
data<2>        |Rtemp<2>       |    7.517|
data<3>        |Rtemp<3>       |    7.507|
data<4>        |Rtemp<4>       |    7.951|
data<5>        |Rtemp<5>       |    7.507|
data<6>        |Rtemp<6>       |    7.517|
data<7>        |Rtemp<7>       |    8.008|
---------------+---------------+---------+

Analysis completed Sun Nov 11 22:54:42 2007
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Peak Memory Usage: 48 MB