clock.twr

16位cpu设计VHDL源码

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml clock clock.ncd -o
clock.twr clock.pcf


Design file:              clock.ncd
Physical constraint file: clock.pcf
Device,speed:             xcv200,-4 (FINAL 1.123 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
T<0>        |   11.324(F)|clkgp             |   0.000|
T<1>        |   11.018(F)|clkgp             |   0.000|
T<2>        |   11.642(F)|clkgp             |   0.000|
T<3>        |   11.018(F)|clkgp             |   0.000|
T<4>        |   10.788(F)|clkgp             |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |         |   13.849|
---------------+---------+---------+---------+---------+

Analysis completed Sun Nov 11 22:38:49 2007
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Peak Memory Usage: 50 MB