pl_fsk.tan.qmsg

来自「基于CPLD」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "y~reg0 x clk 2.343 ns register " "Info: tsu for register \"y~reg0\" (data pin = \"x\", clock pin = \"clk\") is 2.343 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.315 ns + Longest pin register " "Info: + Longest pin to register delay is 5.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns x 1 PIN PIN_AA3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA3; Fanout = 1; PIN Node = 'x'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.689 ns) + CELL(0.539 ns) 5.315 ns y~reg0 2 REG LC_X52_Y1_N7 1 " "Info: 2: + IC(3.689 ns) + CELL(0.539 ns) = 5.315 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.228 ns" { x y~reg0 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 30.59 % ) " "Info: Total cell delay = 1.626 ns ( 30.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.689 ns ( 69.41 % ) " "Info: Total interconnect delay = 3.689 ns ( 69.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.315 ns" { x y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.315 ns" { x x~out0 y~reg0 } { 0.000ns 0.000ns 3.689ns } { 0.000ns 1.087ns 0.539ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.982 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.982 ns y~reg0 2 REG LC_X52_Y1_N7 1 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.154 ns" { clk y~reg0 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.94 % ) " "Info: Total cell delay = 1.370 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 54.06 % ) " "Info: Total interconnect delay = 1.612 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.315 ns" { x y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.315 ns" { x x~out0 y~reg0 } { 0.000ns 0.000ns 3.689ns } { 0.000ns 1.087ns 0.539ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y y~reg0 6.310 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"y~reg0\" is 6.310 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.982 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.982 ns y~reg0 2 REG LC_X52_Y1_N7 1 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.154 ns" { clk y~reg0 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.94 % ) " "Info: Total cell delay = 1.370 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 54.06 % ) " "Info: Total interconnect delay = 1.612 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.172 ns + Longest register pin " "Info: + Longest register to pin delay is 3.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y~reg0 1 REG LC_X52_Y1_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { y~reg0 } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(2.376 ns) 3.172 ns y 2 PIN PIN_V3 0 " "Info: 2: + IC(0.796 ns) + CELL(2.376 ns) = 3.172 ns; Loc. = PIN_V3; Fanout = 0; PIN Node = 'y'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.172 ns" { y~reg0 y } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 74.91 % ) " "Info: Total cell delay = 2.376 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.796 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.796 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.172 ns" { y~reg0 y } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.172 ns" { y~reg0 y } { 0.000ns 0.796ns } { 0.000ns 2.376ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk y~reg0 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 y~reg0 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.172 ns" { y~reg0 y } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.172 ns" { y~reg0 y } { 0.000ns 0.796ns } { 0.000ns 2.376ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q1\[1\] start clk -1.920 ns register " "Info: th for register \"q1\[1\]\" (data pin = \"start\", clock pin = \"clk\") is -1.920 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.982 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.982 ns q1\[1\] 2 REG LC_X52_Y1_N8 3 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N8; Fanout = 3; REG Node = 'q1\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.154 ns" { clk q1[1] } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.94 % ) " "Info: Total cell delay = 1.370 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 54.06 % ) " "Info: Total interconnect delay = 1.612 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk q1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 q1[1] } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.002 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns start 1 PIN PIN_V4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 6; PIN Node = 'start'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.229 ns) + CELL(0.539 ns) 5.002 ns q1\[1\] 2 REG LC_X52_Y1_N8 3 " "Info: 2: + IC(3.229 ns) + CELL(0.539 ns) = 5.002 ns; Loc. = LC_X52_Y1_N8; Fanout = 3; REG Node = 'q1\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.768 ns" { start q1[1] } "NODE_NAME" } } { "PL_FSK.vhd" "" { Text "D:/FPGA最小系统/fsk调制/PL_FSK.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 35.45 % ) " "Info: Total cell delay = 1.773 ns ( 35.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.229 ns ( 64.55 % ) " "Info: Total interconnect delay = 3.229 ns ( 64.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.002 ns" { start q1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.002 ns" { start start~out0 q1[1] } { 0.000ns 0.000ns 3.229ns } { 0.000ns 1.234ns 0.539ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.982 ns" { clk q1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 q1[1] } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.002 ns" { start q1[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.002 ns" { start start~out0 q1[1] } { 0.000ns 0.000ns 3.229ns } { 0.000ns 1.234ns 0.539ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 18 20:44:17 2007 " "Info: Processing ended: Wed Jul 18 20:44:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}