pl_fsk.tan.rpt

基于CPLD

; tsu                                                           ;
+-------+--------------+------------+-------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To     ; To Clock ;
+-------+--------------+------------+-------+--------+----------+
; N/A   ; None         ; 2.343 ns   ; x     ; y~reg0 ; clk      ;
; N/A   ; None         ; 2.183 ns   ; start ; f2     ; clk      ;
; N/A   ; None         ; 2.183 ns   ; start ; f1     ; clk      ;
; N/A   ; None         ; 2.033 ns   ; start ; q2[0]  ; clk      ;
; N/A   ; None         ; 2.032 ns   ; start ; q1[2]  ; clk      ;
; N/A   ; None         ; 2.031 ns   ; start ; q1[3]  ; clk      ;
; N/A   ; None         ; 2.030 ns   ; start ; q1[1]  ; clk      ;
+-------+--------------+------------+-------+--------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 6.310 ns   ; y~reg0 ; y  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+-------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To     ; To Clock ;
+---------------+-------------+-----------+-------+--------+----------+
; N/A           ; None        ; -1.920 ns ; start ; q1[1]  ; clk      ;
; N/A           ; None        ; -1.921 ns ; start ; q1[3]  ; clk      ;
; N/A           ; None        ; -1.922 ns ; start ; q1[2]  ; clk      ;
; N/A           ; None        ; -1.923 ns ; start ; q2[0]  ; clk      ;
; N/A           ; None        ; -2.073 ns ; start ; f2     ; clk      ;
; N/A           ; None        ; -2.073 ns ; start ; f1     ; clk      ;
; N/A           ; None        ; -2.233 ns ; x     ; y~reg0 ; clk      ;
+---------------+-------------+-----------+-------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Wed Jul 18 20:44:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PL_FSK -c PL_FSK --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "q2[0]" and destination register "q1[2]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.409 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N2; Fanout = 4; REG Node = 'q2[0]'
            Info: 2: + IC(0.578 ns) + CELL(0.183 ns) = 0.761 ns; Loc. = LC_X52_Y1_N5; Fanout = 2; COMB Node = 'Add0~104'
            Info: 3: + IC(0.329 ns) + CELL(0.319 ns) = 1.409 ns; Loc. = LC_X52_Y1_N4; Fanout = 3; REG Node = 'q1[2]'
            Info: Total cell delay = 0.502 ns ( 35.63 % )
            Info: Total interconnect delay = 0.907 ns ( 64.37 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.982 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N4; Fanout = 3; REG Node = 'q1[2]'
                Info: Total cell delay = 1.370 ns ( 45.94 % )
                Info: Total interconnect delay = 1.612 ns ( 54.06 % )
            Info: - Longest clock path from clock "clk" to source register is 2.982 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N2; Fanout = 4; REG Node = 'q2[0]'
                Info: Total cell delay = 1.370 ns ( 45.94 % )
                Info: Total interconnect delay = 1.612 ns ( 54.06 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "y~reg0" (data pin = "x", clock pin = "clk") is 2.343 ns
    Info: + Longest pin to register delay is 5.315 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA3; Fanout = 1; PIN Node = 'x'
        Info: 2: + IC(3.689 ns) + CELL(0.539 ns) = 5.315 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'
        Info: Total cell delay = 1.626 ns ( 30.59 % )
        Info: Total interconnect delay = 3.689 ns ( 69.41 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'
        Info: Total cell delay = 1.370 ns ( 45.94 % )
        Info: Total interconnect delay = 1.612 ns ( 54.06 % )
Info: tco from clock "clk" to destination pin "y" through register "y~reg0" is 6.310 ns
    Info: + Longest clock path from clock "clk" to source register is 2.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'
        Info: Total cell delay = 1.370 ns ( 45.94 % )
        Info: Total interconnect delay = 1.612 ns ( 54.06 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.172 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N7; Fanout = 1; REG Node = 'y~reg0'
        Info: 2: + IC(0.796 ns) + CELL(2.376 ns) = 3.172 ns; Loc. = PIN_V3; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 2.376 ns ( 74.91 % )
        Info: Total interconnect delay = 0.796 ns ( 25.09 % )
Info: th for register "q1[1]" (data pin = "start", clock pin = "clk") is -1.920 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N8; Fanout = 3; REG Node = 'q1[1]'
        Info: Total cell delay = 1.370 ns ( 45.94 % )
        Info: Total interconnect delay = 1.612 ns ( 54.06 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.002 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 6; PIN Node = 'start'
        Info: 2: + IC(3.229 ns) + CELL(0.539 ns) = 5.002 ns; Loc. = LC_X52_Y1_N8; Fanout = 3; REG Node = 'q1[1]'
        Info: Total cell delay = 1.773 ns ( 35.45 % )
        Info: Total interconnect delay = 3.229 ns ( 64.55 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 99 megabytes of memory during processing
    Info: Processing ended: Wed Jul 18 20:44:17 2007
    Info: Elapsed time: 00:00:00