📄 pl_fsk.sta.rpt
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TimeQuest Timing Analyzer report for PL_FSK
Wed Jul 18 20:43:24 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Clocks
4. Fmax Summary
5. Setup Summary
6. Hold Summary
7. Minimum Pulse Width
8. Setup Transfers
9. Hold Transfers
10. Unconstrained Paths
11. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name ; PL_FSK ;
; Device Family ; Stratix ;
; Device Name ; EP1S10F484C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+--------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk ; Base ; 1.000 ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+-------------------------+
; Fmax Summary ;
+------------+------------+
; Fmax (MHz) ; Clock Name ;
+------------+------------+
; 634.92 ; clk ;
+------------+------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; clk ; -0.575 ; -1.168 ;
+-------+--------+---------------+
+-------------------------------+
; Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk ; 0.675 ; 0.000 ;
+-------+-------+---------------+
+------------------------------------------------------------------------------+
; Minimum Pulse Width ;
+--------+--------------+----------------+-------+-------+------------+--------+
; Slack ; Actual Width ; Required Width ; Pulse ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-------+-------+------------+--------+
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; y~reg0 ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; y~reg0 ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; f2 ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; f2 ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; f1 ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; f1 ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; q2[0] ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; q2[0] ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; q1[2] ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; q1[2] ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; q1[3] ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; q1[3] ;
; -0.500 ; 0.500 ; 1.000 ; High ; clk ; Rise ; q1[1] ;
; -0.500 ; 0.500 ; 1.000 ; Low ; clk ; Rise ; q1[1] ;
+--------+--------------+----------------+-------+-------+------------+--------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 17 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 17 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 2 ; 2 ;
; Unconstrained Input Port Paths ; 7 ; 7 ;
; Unconstrained Output Ports ; 1 ; 1 ;
; Unconstrained Output Port Paths ; 1 ; 1 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Wed Jul 18 20:43:22 2007
Info: Command: quartus_sta PL_FSK -c PL_FSK
Info: qsta_default_script.tcl version: 23.0.1.4
Warning: Found USE_TIMEQUEST_TIMING_ANALYZER=OFF. The TimeQuest Timing Analyzer is not the default Timing Analysis Tool during full compilation.
Critical Warning: SDC file not found: 'PL_FSK.sdc'
Info: No base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -waveform {0.000 0.500} -name clk clk
Info: Worst-case setup slack is -0.575
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -0.575 -1.168 clk
Info: Worst-case hold slack is 0.675
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.675 0.000 clk
Info: No recovery paths to report
Info: No removal paths to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 101 megabytes of memory during processing
Info: Processing ended: Wed Jul 18 20:43:24 2007
Info: Elapsed time: 00:00:02
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