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📁 用verilog hdl实现的VGA显示彩条信号
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	}
	LINE{
		SIGNAL = "valid";
		INDEX = 68;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
}

VECTOR("E:/VGA_1024×768×85_彩条信号/vga_colour_bar.vwf")
{
	ZOOM{
		ZBEGIN = 0;
		ZEND = 208800;
		NUMERATOR = 528;
		DENOMINATOR = 208800;
		TOP_INDEX = 2;
	}
	CLOCK{
		PERIOD = 10000;
		OFFSET = 0;
		DUTY_CYCLE = 50;
	}
	RANDOM_VALUE{
		INTERVAL_TYPE = HALF_GRID;
	}
	LINE{
		SIGNAL = "clk";
		INDEX = 0;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "rst";
		INDEX = 1;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "enmode";
		INDEX = 2;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "mode";
		INDEX = 3;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "mode[1]";
		INDEX = 4;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "mode[0]";
		INDEX = 5;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R";
		INDEX = 6;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[7]";
		INDEX = 7;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[6]";
		INDEX = 8;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[5]";
		INDEX = 9;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[4]";
		INDEX = 10;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[3]";
		INDEX = 11;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[2]";
		INDEX = 12;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[1]";
		INDEX = 13;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "R[0]";
		INDEX = 14;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B";
		INDEX = 15;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[7]";
		INDEX = 16;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[6]";
		INDEX = 17;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[5]";
		INDEX = 18;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[4]";
		INDEX = 19;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[3]";
		INDEX = 20;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[2]";
		INDEX = 21;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[1]";
		INDEX = 22;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "B[0]";
		INDEX = 23;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G";
		INDEX = 24;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[7]";
		INDEX = 25;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[6]";
		INDEX = 26;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[5]";
		INDEX = 27;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[4]";
		INDEX = 28;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[3]";
		INDEX = 29;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[2]";
		INDEX = 30;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[1]";
		INDEX = 31;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "G[0]";
		INDEX = 32;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "Cblank";
		INDEX = 33;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "Hsync";
		INDEX = 34;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "Vsync";
		INDEX = 35;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt";
		INDEX = 36;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[10]";
		INDEX = 37;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[9]";
		INDEX = 38;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[8]";
		INDEX = 39;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[7]";
		INDEX = 40;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[6]";
		INDEX = 41;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[5]";
		INDEX = 42;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[4]";
		INDEX = 43;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[3]";
		INDEX = 44;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[2]";
		INDEX = 45;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[1]";
		INDEX = 46;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_cnt[0]";
		INDEX = 47;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt";
		INDEX = 48;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[10]";
		INDEX = 49;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[9]";
		INDEX = 50;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[8]";
		INDEX = 51;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[7]";
		INDEX = 52;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[6]";
		INDEX = 53;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[5]";
		INDEX = 54;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[4]";
		INDEX = 55;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[3]";
		INDEX = 56;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[2]";
		INDEX = 57;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[1]";
		INDEX = 58;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_cnt[0]";
		INDEX = 59;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_state";
		INDEX = 60;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_state[2]";
		INDEX = 61;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_state[1]";
		INDEX = 62;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "h_state[0]";
		INDEX = 63;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_state";
		INDEX = 64;
		FORMAT = T;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_state[2]";
		INDEX = 65;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_state[1]";
		INDEX = 66;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "v_state[0]";
		INDEX = 67;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
	LINE{
		SIGNAL = "valid";
		INDEX = 68;
		FORMAT = E;
		SCALE = 1;
		VISIBLE = Y;
		FLAG = N;
	}
}
上一页 12
💿 文件大小 441 K
👤 上传用户 houlong111
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#verilog #hdl #VGA #信号
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