wr_sector.vhd

这是异步FIFO的VHDL实现代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity wr_sector is
  generic(width:integer:=8);
  port(wr_clk,wren,clr,wr_add_co:in std_logic;
       wr_add:in std_logic_vector(width-1 downto 0);    
       wr_rd_add_grey:in std_logic_vector(width downto 0); --读模块来的grey             
       wr_add_grey:out std_logic_vector(width downto 0);--写模块产生的写地址格雷码以及写地址进位码
       full,al_full:out std_logic
     ); 
end entity;

architecture rtl of wr_sector is
   
   signal wadd,waddp,wadd_grey,wadd_grey_temp,wr_radd_grey,wr_rd_grey,
          wr_radd_temp,wr_radd,radd_grey:std_logic_vector(width-1 downto 0);
   signal wadd_co,wr_rd_add_co:std_logic;
   signal wr_rd_add_greyp:std_logic_vector(width downto 0);
 

   component norm_to_grey 
       port(din:in std_logic_vector(width-1 downto 0);
            dout:out std_logic_vector(width-1 downto 0)
           );
   end component;

   component grey_to_norm
        port(din:in std_logic_vector(width-1 downto 0);
             dout:out std_logic_vector(width-1 downto 0)
            );
   end component;

   component dffx
       port(din:in std_logic_vector(width-1 downto 0);
            clk:in std_logic;
            dout:out std_logic_vector(width-1 downto 0));
   end component;
   
begin 
    
    
--写地址产生模块，此程序同时产生写地址的自然码和格雷码:wadd,wadd_grey,wadd_co
    waddp<=wr_add;             
    wr_add_grey<=wadd_co&wadd_grey;
       
--wr_addr_out<=wadd; 
       -- waddp<=wadd+1; 
        u1:norm_to_grey port map(waddp,wadd_grey_temp);
        wadd_process:process(clr,wr_clk)
            begin
                if clr='1' then
                   wadd<=(others=>'0');
                   wadd_grey<=(others=>'0');
                   wadd_co<='0';
                elsif wr_clk'event and wr_clk='1' then
                    if wren='1' then
                       wadd<=waddp;
                       wadd_grey<=wadd_grey_temp;
                       wadd_co<=wr_add_co;
                    end if;
                end if;
         end process;

--获取写时钟采样的自然码和格雷码的读地址:wr_radd,wr_radd_grey,wr_radd_co
        u3:dffx port map(wr_rd_add_grey,wr_clk,wr_rd_add_greyp);
        wr_rd_grey<=wr_rd_add_greyp(width-1 downto 0);
        wr_rd_add_co<= wr_rd_add_greyp(width);       

        u2:grey_to_norm port map(wr_rd_grey,wr_radd_temp);
        process(clr,wr_clk)
            begin
                if clr='1' then
                    wr_radd_grey<=(others=>'0');
                    wr_radd<=(Others=>'0');
                    wr_radd_co<='0';
                elsif wr_clk'event and wr_clk='1' then
                    wr_radd_grey<=wr_rd_add_greyp;-----
                    wr_radd<=wr_radd_temp;
                    wr_radd_co<=wr_rd_add_co;
                end if;
        end process;

--满标志产生模块
      -- wr_compare<=wr_radd-wadd;
       full_process:process(clr,wr_clk)
           begin
               if clr='1' then
                   full<='0';
               elsif wr_clk'event and wr_clk='1' then
               
                       if((wr_radd-wadd=1)and(wadd_co/=wr_radd_co))  or
                          ((wr_radd="00000000"and wadd="11111111")) then 
                           full<='1';
                       else 
                           full<='0';
                       end if;                  
              end if;
       end process;

--将满标志产生模块
       
       half_full_process:process(clr,wr_clk)
           begin
               if(clr='1') then
                   al_full<='0';
               elsif wr_clk'event and wr_clk='1' then
                  if(wadd_co/=wr_radd_co)then
                    if((wadd>=0 and wadd<=246) and (wr_radd-wadd=9))or
                         ((wadd>246 and wadd<=255) and (wadd-wr_radd=247)) then


                      --if((wr_radd>=0 and wr_radd<=206) and (wadd-wr_radd=49))or
                        -- ((wr_radd>206 and wr_radd<=255) and (wr_radd-wadd=207)) then
                 
                       --if (((wr_radd>="00000000" and wr_radd<="01000100")and(wadd-wr_radd="10111011"))
                          --or((wr_radd>"01000100" and wr_radd<="11111111")and(wr_radd-wadd="01000101"))) then
                           al_full<='1';
                       else 
                           al_full<='0';
                       end if;
                 end if;
                  
                  
               end if;
       end process;
end architecture;