📄 division3.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC30 |LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node1
| +--------------------------- LC29 |LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node3
| | +------------------------- LC28 |LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node1
| | | +----------------------- LC27 |LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node3
| | | | +--------------------- LC26 out1
| | | | | +------------------- LC25 temp13
| | | | | | +----------------- LC24 temp12
| | | | | | | +--------------- LC23 temp11
| | | | | | | | +------------- LC22 temp10
| | | | | | | | | +----------- LC21 division2
| | | | | | | | | | +--------- LC20 temp23
| | | | | | | | | | | +------- LC19 temp22
| | | | | | | | | | | | +----- LC18 temp21
| | | | | | | | | | | | | +--- LC17 temp20
| | | | | | | | | | | | | | +- LC31 division4
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC30 -> - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node1
LC29 -> - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node3
LC28 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node1
LC27 -> - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node3
LC25 -> - * - - - * - * * * - - - - - | - * | <-- temp13
LC24 -> - * - - - * * * * * - - - - - | - * | <-- temp12
LC23 -> * * - - - * * * * * - - - - - | - * | <-- temp11
LC22 -> * * - - - * * * * * - - - - - | - * | <-- temp10
LC21 -> - - - - * - - - - * - - - - - | - * | <-- division2
LC20 -> - - - * - - - - - - * - * * * | - * | <-- temp23
LC19 -> - - - * - - - - - - * * * * * | - * | <-- temp22
LC18 -> - - * * - - - - - - * * * * * | - * | <-- temp21
LC17 -> - - * * - - - - - - * * * * * | - * | <-- temp20
LC31 -> - - - - * - - - - - - - - - * | - * | <-- division4
Pin
4 -> - - - - - * * * * * * * * * * | - * | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\suocun\division3.rpt
division3
** EQUATIONS **
clk : INPUT;
-- Node name is ':7' = 'division2'
-- Equation name is 'division2', location is LC021, type is buried.
division2 = TFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = division2 & !temp10 & temp11 & !temp12 & !temp13
# !division2 & temp10 & !temp11 & !temp12 & !temp13;
-- Node name is ':12' = 'division4'
-- Equation name is 'division4', location is LC031, type is buried.
division4 = TFFE( _EQ002, !clk, VCC, VCC, VCC);
_EQ002 = division4 & !temp20 & temp21 & !temp22 & !temp23
# !division4 & temp20 & !temp21 & !temp22 & !temp23;
-- Node name is 'out1'
-- Equation name is 'out1', location is LC026, type is output.
out1 = LCELL( _EQ003 $ VCC);
_EQ003 = !division2 & !division4;
-- Node name is ':6' = 'temp10'
-- Equation name is 'temp10', location is LC022, type is buried.
temp10 = TFFE(!_EQ004, clk, VCC, VCC, VCC);
_EQ004 = !temp10 & temp11 & !temp12 & !temp13;
-- Node name is ':5' = 'temp11'
-- Equation name is 'temp11', location is LC023, type is buried.
temp11 = DFFE( _EQ005 $ _LC030, clk, VCC, VCC, VCC);
_EQ005 = _LC030 & !temp10 & temp11 & !temp12 & !temp13;
-- Node name is ':4' = 'temp12'
-- Equation name is 'temp12', location is LC024, type is buried.
temp12 = TFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = temp10 & temp11;
-- Node name is ':3' = 'temp13'
-- Equation name is 'temp13', location is LC025, type is buried.
temp13 = DFFE( _EQ007 $ _LC029, clk, VCC, VCC, VCC);
_EQ007 = _LC029 & !temp10 & temp11 & !temp12 & !temp13;
-- Node name is ':11' = 'temp20'
-- Equation name is 'temp20', location is LC017, type is buried.
temp20 = TFFE(!_EQ008, !clk, VCC, VCC, VCC);
_EQ008 = !temp20 & temp21 & !temp22 & !temp23;
-- Node name is ':10' = 'temp21'
-- Equation name is 'temp21', location is LC018, type is buried.
temp21 = DFFE( _EQ009 $ _LC028, !clk, VCC, VCC, VCC);
_EQ009 = _LC028 & !temp20 & temp21 & !temp22 & !temp23;
-- Node name is ':9' = 'temp22'
-- Equation name is 'temp22', location is LC019, type is buried.
temp22 = TFFE( _EQ010, !clk, VCC, VCC, VCC);
_EQ010 = temp20 & temp21;
-- Node name is ':8' = 'temp23'
-- Equation name is 'temp23', location is LC020, type is buried.
temp23 = DFFE( _EQ011 $ _LC027, !clk, VCC, VCC, VCC);
_EQ011 = _LC027 & !temp20 & temp21 & !temp22 & !temp23;
-- Node name is '|LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( temp11 $ temp10);
-- Node name is '|LPM_ADD_SUB:50|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( temp13 $ _EQ012);
_EQ012 = temp10 & temp11 & temp12;
-- Node name is '|LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( temp21 $ temp20);
-- Node name is '|LPM_ADD_SUB:231|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( temp23 $ _EQ013);
_EQ013 = temp20 & temp21 & temp22;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\suocun\division3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 30,114K
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