📄 automake.log
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Number of GCLKs 2 out of 4 50%Overall effort level (-ol): 2 (set by user)Placer effort level (-pl): 2 (set by user)Placer cost table entry (-t): 1Router effort level (-rl): 2 (set by user)Extra effort level (-xe): 0 (set by user)Starting initial Timing Analysis. REAL time: 3 secs Finished initial Timing Analysis. REAL time: 4 secs WARNING:Place:1864 - The placement of the source component LVDS must be in the same CLB column as the asynchronus output ddrc/qsel IOB pair ck_x and ck. This will minimize the skew issues involving the top and bottom edges.WARNING:Place:1864 - The placement of the source component LVDS must be in the same CLB column as the asynchronus output ddra/qsel IOB pair da_x and da. This will minimize the skew issues involving the top and bottom edges.WARNING:Place:1864 - The placement of the source component LVDS must be in the same CLB column as the asynchronus output ddrb/qsel IOB pair db_x and db. This will minimize the skew issues involving the top and bottom edges.The following table is the list of pairs of sites, whether the site isoccupied, and capable of asynchronous output or not.Postive/Master | asynchronous | Occupied | Negative/Slave | Occupied--------------------------------------------------------------------P213 | no | yes | P215 | no P210 | no | no | P209 | no P89 | no | yes | P87 | no P92 | no | no | P93 | no P236 | no | no | P237 | no P234 | yes | no | P235 | no P228 | yes | no | P229 | no P223 | yes | no | P224 | no P220 | yes | no | P221 | no P217 | yes | no | P218 | no P209 | no | no | P215 | no P205 | yes | no | P206 | no P202 | yes | no | P203 | no P199 | yes | no | P200 | no P194 | yes | no | P195 | no P191 | yes | no | P192 | no P188 | yes | no | P189 | no P186 | no | no | P187 | no P184 | yes | no | P185 | no P178 | yes | no | P177 | no P174 | yes | no | P173 | no P171 | yes | no | P170 | no P168 | yes | no | P167 | no P163 | yes | no | P162 | no P160 | yes | no | P159 | no P157 | yes | no | P156 | no P155 | no | no | P154 | no P153 | yes | no | P152 | no P145 | yes | no | P144 | no P142 | yes | no | P141 | no P139 | yes | no | P138 | no P134 | yes | no | P133 | no P131 | yes | no | P130 | no P128 | yes | no | P127 | no P126 | no | no | P125 | no P124 | yes | no | P123 | no P118 | yes | yes | P117 | yes P114 | yes | yes | P113 | yes P111 | yes | yes | P110 | yes P108 | yes | no | P107 | no P103 | yes | no | P102 | no P100 | yes | no | P99 | no P97 | yes | no | P96 | no P95 | no | no | P94 | no P93 | no | no | P87 | no P84 | no | no | P82 | no P79 | yes | no | P78 | no P74 | yes | no | P73 | no P71 | yes | no | P70 | no P68 | yes | no | P67 | no P66 | no | no | P65 | no P64 | yes | no | P63 | no P56 | yes | no | P57 | no P52 | yes | no | P53 | no P49 | yes | no | P50 | no P46 | yes | no | P47 | no P41 | yes | no | P42 | no P38 | yes | no | P39 | no P35 | yes | no | P36 | no P33 | no | no | P34 | no P27 | yes | no | P28 | no P23 | yes | no | P24 | no P20 | yes | no | P21 | no P17 | yes | no | P18 | no P12 | yes | no | P13 | no P9 | yes | no | P10 | no P6 | yes | no | P7 | no P4 | no | no | P5 | no Design passed SelectIO DRC.WARNING:Place:1807 - MAXSKEW constraint detected. Use of a tight MAXSKEW constraint especially in conjunction with a PERIOD, MAXDELAY or FROM TO constraint may significantly increase Place and Route runtime. MAXSKEW will not effect the Global Buffered nets. To direct PAR to route a net on the Secondary Low Skew Lines use the constraint 'NET USELOWSKEWLINES;' in the User Constraints File(UCF).Starting the placer. REAL time: 5 secs Placement pass 1 ..Placer score = 3375Placement pass 2 .Placer score = 8072Placement pass 3 ..Placer score = 7448Placement pass 4 ..Placer score = 7289Optimizing ... Placer score = 5996Placer score = 5590Placer score = 5323Placer score = 5210Placer score = 5046Placer score = 4957Placer score = 4895Placer score = 4896Placer score = 4880Placer score = 4851Placer stage completed in real time: 7 secs All IOBs have been constrained to specific sites.Select IO Utilization and Usage Summary_______________________________________NR - means Not Required.Each Group of a specific Standard is listed. IO standard (LVDS Vref=NR Vcco=2.50) uses 6 components (6 currently placed). (0 - Inputs, 6 - Outputs, 0 - Bidirectional)IO standard (LVTTL Vref=NR Vcco=3.30) uses 2 components (2 currently placed). (2 - Inputs, 0 - Outputs, 0 - Bidirectional)Bank Summary____________If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' atthe end of a summary row. IOBs can be placed in a bank's Vref sites when none ofthe IOBs in the bank require a Vref site.NR - means Not RequiredBank 0 has 19 pads, 1 (5%) are utilized, with 7 possible dedicated Vref sites.Vref should be set to NR volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ clk I LVTTL NR 3.30 GCLKPAD3 P213 None Bank 4 has 21 pads, 6 (28%) are utilized, with 7 possible dedicated Vref sites.Vcco should be set to 2.50 volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ db_x O LVDS 2.50 PAD385 P118 None db O LVDS 2.50 PAD386 P117 None ck_x O LVDS 2.50 PAD407 P114 None ck O LVDS 2.50 PAD408 P113 None da_x O LVDS 2.50 PAD409 P111 None Vref da O LVDS 2.50 PAD410 P110 None Bank 5 has 20 pads, 1 (5%) are utilized, with 7 possible dedicated Vref sites.Vref should be set to NR volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ clk4x I LVTTL NR 3.30 GCLKPAD1 P89 None Placer completed in real time: 8 secs Dumping design to file tx2bit.ncd.Total REAL time to Placer completion: 8 secs Total CPU time to Placer completion: 4 secs 0 connection(s) routed; 103 unrouted.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 8 secs Starting iterative routing. Routing active signals...........End of iteration 1 103 successful; 0 unrouted; (0) REAL time: 9 secs Constraints are met. Total REAL time: 9 secs Total CPU time: 6 secs End of route. 103 routed (100.00%); 0 unrouted.No errors found. Completely routed. Total REAL time to Router completion: 9 secs Total CPU time to Router completion: 6 secs Generating PAR statistics.Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- NET "ddra/qrise" MAXDELAY = 600 pS | 0.600ns | 0.237ns | -------------------------------------------------------------------------------- NET "ddra/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddra/qfall" MAXDELAY = 600 pS | 0.600ns | 0.234ns | -------------------------------------------------------------------------------- NET "ddra/qfall" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddra/crr" MAXDELAY = 600 pS | 0.600ns | 0.364ns | -------------------------------------------------------------------------------- NET "ddra/crf" MAXDELAY = 600 pS | 0.600ns | 0.438ns | -------------------------------------------------------------------------------- NET "ddrb/qrise" MAXDELAY = 600 pS | 0.600ns | 0.537ns | -------------------------------------------------------------------------------- NET "ddrb/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrb/qfall" MAXDELAY = 600 pS | 0.600ns | 0.361ns | -------------------------------------------------------------------------------- NET "ddrb/qfall" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrb/crr" MAXDELAY = 600 pS | 0.600ns | 0.471ns | -------------------------------------------------------------------------------- NET "ddrb/crf" MAXDELAY = 600 pS | 0.600ns | 0.385ns | -------------------------------------------------------------------------------- NET "ddrc/qrise" MAXDELAY = 600 pS | 0.600ns | 0.364ns | -------------------------------------------------------------------------------- NET "ddrc/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrc/crr" MAXDELAY = 600 pS | 0.600ns | 0.234ns | -------------------------------------------------------------------------------- NET "ddrc/crf" MAXDELAY = 600 pS | 0.600ns | 0.450ns | -------------------------------------------------------------------------------- TS_clk4x = PERIOD TIMEGRP "clk4x" 2 nS | | | HIGH 50.000000 % | | | -------------------------------------------------------------------------------- TS_clk = PERIOD TIMEGRP "clk" 8 nS HIG | | | H 50.000000 % | | | -------------------------------------------------------------------------------- TS_FST2FST = MAXDELAY FROM TIMEGRP "FASTC | 3.800ns | 2.911ns | 2 LOCK" TO TIMEGRP "FASTCLOCK" 3.800 nS | | | -------------------------------------------------------------------------------- TS_FST2LAT = MAXDELAY FROM TIMEGRP "FASTC | | | LOCK" TO TIMEGRP "FASELATCH" 3.800 nS | | | -------------------------------------------------------------------------------- TS_LAT2LAT = MAXDELAY FROM TIMEGRP "FASEL | 3.800ns | 2.283ns | 2 ATCH" TO TIMEGRP "FASELATCH" 3.800 nS | | | -------------------------------------------------------------------------------- TS_SLO2FST = MAXDELAY FROM TIMEGRP "SLOWC | 8.000ns | 2.482ns | 2 LOCK" TO TIMEGRP "FASTCLOCK" 8 nS | | | --------------------------------------------------------------------------------All constraints were met.Dumping design to file tx2bit.ncd.All signals are completely routed.Total REAL time to PAR completion: 11 secs Total CPU time to PAR completion: 7 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.Tcl D:/Xilinx/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.PAR completed successfullyDone: completed successfully.
Launching: 'exewrap -tcl -command __launchTA.tcl'
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