automake.log

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
=========================================================================
Final Results
Top Level Output File Name         : tx2bit
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : virtexe
Keep Hierarchy                     : YES
Macro Generator                    : macro+

Design Statistics
# IOs                              : 8

Cell Usage :
# BELS                             : 25
#      GND                         : 16
#      INV                         : 4
#      LUT1                        : 3
#      VCC                         : 2
# FlipFlops/Latches                : 41
#      FD                          : 6
#      FD_1                        : 7
#      FDC                         : 18
#      FDR                         : 2
#      FDR_1                       : 1
#      LD                          : 3
#      LD_1                        : 3
#      LDC_1                       : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 6
#      OBUF_LVDS                   : 6
# Logical                          : 48
#      AND2                        : 15
#      AND2b1                      : 15
#      OR2                         : 15
#      XOR2                        : 3
# Others                           : 18
#      FMAP                        : 18
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk4x                              | BUFGP                  | 7     |
clk                                | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.752ns (Maximum Frequency: 128.999MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.351ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk4x'
Delay:               3.876ns (Levels of Logic = 1)
  Source:            ddrb/ddr_ld2
  Destination:       ddrb/ddr_ld1
  Source Clock:      clk4x rising
  Destination Clock: clk4x falling

  Data Path: ddrb/ddr_ld2 to ddrb/ddr_ld1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    LD_1:G->Q              2   1.091   1.072  ddr_ld2 (lrf)
    INV:I->O               1   0.468   0.920  ddr_inv (inv_lrf)
    LD:D                       0.325          ddr_ld1
    ----------------------------------------
    Total                      3.876ns (1.884ns logic, 1.992ns route)
                                       (48.6% logic, 51.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk4x'
Offset:              9.351ns (Levels of Logic = 5)
  Source:            ddrc/ddr_fd4
  Destination:       ck_x
  Source Clock:      clk4x rising

  Data Path: ddrc/ddr_fd4 to ck_x
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FD_1:C->Q              1   0.992   0.920  ddr_fd4 (crf)
    XOR2:I0->O             2   0.468   1.072  ddr_xor (qsel)
     begin scope: 'ddr_m'
    AND2:I0->O             1   0.468   0.920  U1 (M1)
    OR2:I0->O              2   0.468   1.072  U2 (o)
     end scope: 'ddr_m'
     end scope: 'ddrc'
    LUT1:I0->O             1   0.468   0.920  I_INV_c (cn)
    OBUF_LVDS:I->O             1.583          data_cn (ck_x)
    ----------------------------------------
    Total                      9.351ns (4.447ns logic, 4.904ns route)
                                       (47.6% logic, 52.4% route)

=========================================================================
CPU : 5.86 / 6.11 s | Elapsed : 6.00 / 6.00 s
 
--> 
EXEWRAP detected that program 'D:/Xilinx/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.2i - ngdbuild E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd e:/work/6_1pro/_ngo -nt timestamp -uc
E:\work\6-1\tx2bit.ucf -p xcv1000e-hq240-6 tx2bit.ngc tx2bit.ngd 

Reading NGO file "E:/work/6_1pro/tx2bit.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "E:/work/6-1/tx2bit.ucf" ...
INFO:NgdBuild:678 - The constraint for NET 'ddra/qrise' is being attached to the
   equivalent NET 'ddra/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddra/qrise' is being attached to the
   equivalent NET 'ddra/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddra/qfall' is being attached to the
   equivalent NET 'ddra/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddra/qfall' is being attached to the
   equivalent NET 'ddra/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddra/crr' is being attached to the
   equivalent NET 'ddra/crr'.
INFO:NgdBuild:678 - The constraint for NET 'ddra/crf' is being attached to the
   equivalent NET 'ddra/crf'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/qrise' is being attached to the
   equivalent NET 'ddrb/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/qrise' is being attached to the
   equivalent NET 'ddrb/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/qfall' is being attached to the
   equivalent NET 'ddrb/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/qfall' is being attached to the
   equivalent NET 'ddrb/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/crr' is being attached to the
   equivalent NET 'ddrb/crr'.
INFO:NgdBuild:678 - The constraint for NET 'ddrb/crf' is being attached to the
   equivalent NET 'ddrb/crf'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/qrise' is being attached to the
   equivalent NET 'ddrc/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/qrise' is being attached to the
   equivalent NET 'ddrc/qrise'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/qfall' is being attached to the
   equivalent NET 'ddrc/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/qfall' is being attached to the
   equivalent NET 'ddrc/qfall'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/crr' is being attached to the
   equivalent NET 'ddrc/crr'.
INFO:NgdBuild:678 - The constraint for NET 'ddrc/crf' is being attached to the
   equivalent NET 'ddrc/crf'.

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "tx2bit.ngd" ...

Writing NGDBUILD log file "tx2bit.bld"...

NGDBUILD done.
EXEWRAP detected that program 'ngdbuild' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'


Creating TCL Process
Starting: 'map -f _map.rsp'


Release 4.2i - Map E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Using target part "v1000ehq240-6".
Removing unused or disabled logic...
Running cover...
Writing file tx2bit.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "tx2bit.ncd"...

Design Summary:
   Number of errors:      0
   Number of warnings:    2
   Number of Slices:                 36 out of 12,288    1%
   Number of Slices containing
      unrelated logic:                0 out of     36    0%
   Total Number Slice Registers:     38 out of 24,576    1%
      Number used as Flip Flops:                   31
      Number used as Latches:                       7
   Number of 4 input LUTs:           17 out of 24,576    1%
   Number of bonded IOBs:             6 out of    158    3%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
Total equivalent gate count for design:  385
Additional JTAG gate count for IOBs:  384

Mapping completed.
See MAP report file "tx2bit.mrp" for details.
Tcl D:/Xilinx/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_nc1TOncd_exewrap.rsp'


Creating TCL Process
Found _prepar.rsp
Starting: 'par -f _par.rsp'


Release 4.2i - Par E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".


Constraints file: tx2bit.pcf

Loading design for application par from file par_temp.ncd.
   "tx2bit" is an NCD, version 2.37, device xcv1000e, package hq240, speed -6
Loading device for application par from file 'v1000e.nph' in environment
D:/Xilinx.
Device speed data version:  PRELIMINARY 1.65 2001-12-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs             6 out of 158     3%
      Number of LOCed External IOBs    6 out of 6     100%

   Number of SLICEs                   36 out of 12288   1%