__projnav.log

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

Updating: Floorplan Design

Starting: 'exewrap @__mapFloorPlannerAppExewrap.rsp'


Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Text-based Post-Place & Route Static Timing Report

Starting: 'exewrap @_ncdTOtwr_exewrap.rsp'


Creating TCL Process
Starting: 'trce -f __posttrc.rsp tx2bit.ncd -o tx2bit.twr tx2bit.pcf'


Release 4.2i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.



Loading design for application trce from file tx2bit.ncd.
   "tx2bit" is an NCD, version 2.37, device xcv1000e, package hq240, speed -6
Loading device for application trce from file 'v1000e.nph' in environment
D:/Xilinx.
--------------------------------------------------------------------------------
Release 4.2i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce -e 3 -l 3 -xml tx2bit tx2bit.ncd -o tx2bit.twr tx2bit.pcf

Design file:              tx2bit.ncd
Physical constraint file: tx2bit.pcf
Device,speed:             xcv1000e,-6 (PRELIMINARY 1.65 2001-12-19)
Report level:             error report
--------------------------------------------------------------------------------

WARNING:Timing:2491 - No timing constraints found, doing default enumeration.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 126 paths, 66 nets, and 123 connections (100.0% coverage)

Design statistics:
   Minimum period:   7.449ns (Maximum frequency: 134.246MHz)
   Maximum combinational path delay:  12.881ns
   Maximum net delay:   8.602ns


Analysis completed Sun Dec 15 15:13:49 2002
--------------------------------------------------------------------------------

Generating Report ...

Total time: 5 secs 
Tcl D:/Xilinx/data/projnav/_postRouteTiming.tcl detected that program 'trce -f __posttrc.rsp tx2bit.ncd -o tx2bit.twr tx2bit.pcf' completed successfully.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Map

Starting: 'exewrap @__tx2bit_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx/bin/nt/xst.exe -ifn tx2bit.xst -ofn tx2bit.syr'


Starting: 'D:/Xilinx/bin/nt/xst.exe -ifn tx2bit.xst -ofn tx2bit.syr '


Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter overwrite set to YES
CPU : 0.01 / 0.22 s | Elapsed : 0.00 / 1.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : tx2bit.prj

---- Target Parameters
Target Device                      : xcv1000e-hq240-6
Output File Name                   : tx2bit
Output Format                      : NGC
Target Technology                  : virtexe

---- Source Options
Top Module Name                    : tx2bit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No

=========================================================================

 
Compiling source file : tx2bit.prj
Compiling included source file '../6-1/m2_1.v'
Module <m2_1> compiled.
Continuing compilation of source file 'tx2bit.prj'
Compiling included source file '../6-1/ddrfd.v'
Module <ddrfd> compiled.
Continuing compilation of source file 'tx2bit.prj'
Compiling included source file '../6-1/load_gen.v'
Module <load_gen> compiled.
Continuing compilation of source file 'tx2bit.prj'
Compiling included source file '../6-1/piso.v'
Module <piso> compiled.
Continuing compilation of source file 'tx2bit.prj'
Compiling included source file '../6-1/tx2bit.v'
Module <tx2bit> compiled.
Continuing compilation of source file 'tx2bit.prj'
Compiling included source file 'D:/Xilinx/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'tx2bit.prj'
No errors in compilation
Analysis of file <tx2bit.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing module <OBUF_LVDS>.
 
Analyzing module <FMAP>.
 
Analyzing module <XOR2>.
 
Analyzing module <OR2>.
 
Analyzing module <AND2>.
 
Analyzing module <AND2B1>.
 
Analyzing module <GND>.
 
Analyzing module <m2_1>.
Module <m2_1> is correct for synthesis.
 
Analyzing module <INV>.
 
Analyzing module <FD_1>.
 
Analyzing module <FD>.
 
Analyzing module <LD_1>.
 
Analyzing module <LD>.
 
Analyzing module <ddrfd>.
Module <ddrfd> is correct for synthesis.
 
Analyzing module <FDR_1>.
 
Analyzing module <LDC_1>.
 
Analyzing module <FDC>.
 
Analyzing module <FDR>.
 
Analyzing module <VCC>.
 
Analyzing module <load_gen>.
Module <load_gen> is correct for synthesis.
 
Analyzing module <piso>.
Module <piso> is correct for synthesis.
 
Analyzing top module <tx2bit>.
Module <tx2bit> is correct for synthesis.

Synthesizing Unit <m2_1>.
    Related source file is ../6-1/m2_1.v.
Unit <m2_1> synthesized.


Synthesizing Unit <ddrfd>.
    Related source file is ../6-1/ddrfd.v.
Unit <ddrfd> synthesized.


Synthesizing Unit <load_gen>.
    Related source file is ../6-1/load_gen.v.
Unit <load_gen> synthesized.


Synthesizing Unit <piso>.
    Related source file is ../6-1/piso.v.
Unit <piso> synthesized.


Synthesizing Unit <tx2bit>.
    Related source file is ../6-1/tx2bit.v.
Unit <tx2bit> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================


Starting low level synthesis...
Optimizing unit <tx2bit> ...

Building and optimizing final netlist ...

WARNING:Xst:387 - The KEEP property attached to the net <a> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <b> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <c> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddra_ddr_m_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddra_ddr_m_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddra_inv_lrf> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddra_qsel> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrb_ddr_m_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrb_ddr_m_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrb_inv_lrf> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrb_qsel> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrc_ddr_m_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrc_ddr_m_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrc_inv_lrf> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <ddrc_qsel> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_m_0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_m_1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_m_2> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux1_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux1_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux2_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux2_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux3_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso1_mux3_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_m_0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_m_1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_m_2> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux1_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux1_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux2_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux2_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux3_M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso2_mux3_M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <piso3_m_0> may hinder timing optimization.
   You may achieve better results by removing this property