__projnav.log

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            22 out of 158    13%
      Number of LOCed External IOBs    6 out of 22     27%

   Number of SLICEs                   37 out of 12288   1%

   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

WARNING:Place:1864 - The placement of the source component LVDS must be in the
   same CLB column as the asynchronus output ddra_qsel IOB pair da_x and da.
   This will minimize the skew issues involving the top and bottom edges.
WARNING:Place:1864 - The placement of the source component LVDS must be in the
   same CLB column as the asynchronus output ddrc_qsel IOB pair ck_x and ck.
   This will minimize the skew issues involving the top and bottom edges.
WARNING:Place:1864 - The placement of the source component LVDS must be in the
   same CLB column as the asynchronus output ddrb_qsel IOB pair db_x and db.
   This will minimize the skew issues involving the top and bottom edges.

The following table is the list of pairs of sites, whether the site is
occupied, and capable of asynchronous output or not.

Postive/Master | asynchronous | Occupied | Negative/Slave | Occupied
--------------------------------------------------------------------
P213           | no           | no       | P215           | no      
P210           | no           | no       | P209           | no      
P89            | no           | no       | P87            | no      
P92            | no           | no       | P93            | no      
P236           | no           | no       | P237           | no      
P234           | yes          | no       | P235           | no      
P228           | yes          | no       | P229           | no      
P223           | yes          | no       | P224           | no      
P220           | yes          | no       | P221           | no      
P217           | yes          | no       | P218           | no      
P209           | no           | no       | P215           | no      
P205           | yes          | no       | P206           | no      
P202           | yes          | no       | P203           | no      
P199           | yes          | no       | P200           | no      
P194           | yes          | no       | P195           | no      
P191           | yes          | no       | P192           | no      
P188           | yes          | no       | P189           | no      
P186           | no           | no       | P187           | no      
P184           | yes          | no       | P185           | no      
P178           | yes          | no       | P177           | no      
P174           | yes          | no       | P173           | no      
P171           | yes          | no       | P170           | no      
P168           | yes          | no       | P167           | no      
P163           | yes          | no       | P162           | no      
P160           | yes          | no       | P159           | no      
P157           | yes          | no       | P156           | no      
P155           | no           | no       | P154           | no      
P153           | yes          | no       | P152           | no      
P145           | yes          | no       | P144           | no      
P142           | yes          | no       | P141           | no      
P139           | yes          | no       | P138           | no      
P134           | yes          | no       | P133           | no      
P131           | yes          | no       | P130           | no      
P128           | yes          | no       | P127           | no      
P126           | no           | no       | P125           | no      
P124           | yes          | no       | P123           | no      
P118           | yes          | yes      | P117           | yes     
P114           | yes          | yes      | P113           | yes     
P111           | yes          | yes      | P110           | yes     
P108           | yes          | no       | P107           | no      
P103           | yes          | no       | P102           | no      
P100           | yes          | no       | P99            | no      
P97            | yes          | no       | P96            | no      
P95            | no           | no       | P94            | no      
P93            | no           | no       | P87            | no      
P84            | no           | no       | P82            | no      
P79            | yes          | no       | P78            | no      
P74            | yes          | no       | P73            | no      
P71            | yes          | no       | P70            | no      
P68            | yes          | no       | P67            | no      
P66            | no           | no       | P65            | no      
P64            | yes          | no       | P63            | no      
P56            | yes          | no       | P57            | no      
P52            | yes          | no       | P53            | no      
P49            | yes          | no       | P50            | no      
P46            | yes          | no       | P47            | no      
P41            | yes          | no       | P42            | no      
P38            | yes          | no       | P39            | no      
P35            | yes          | no       | P36            | no      
P33            | no           | no       | P34            | no      
P27            | yes          | no       | P28            | no      
P23            | yes          | no       | P24            | no      
P20            | yes          | no       | P21            | no      
P17            | yes          | no       | P18            | no      
P12            | yes          | no       | P13            | no      
P9             | yes          | no       | P10            | no      
P6             | yes          | no       | P7             | no      
P4             | no           | no       | P5             | no      

Design passed SelectIO DRC.
Starting initial Placement phase. REAL time: 4 secs 
Finished initial Placement phase. REAL time: 4 secs 
Starting the placer. REAL time: 4 secs 
Placement pass 1 .
Placer score = 13185
Placement pass 2 .
Placer score = 9465
Optimizing ... 
Placer score = 7365
Placer score = 13125

Select IO Utilization and Usage Summary
_______________________________________

NR - means Not Required.
Each Group of a specific Standard is listed. 

IO standard (LVDS Vref=NR Vcco=2.50) uses 6 components (6 currently placed).
  (0 - Inputs, 6 - Outputs, 0 - Bidirectional)
IO standard (LVTTL Vref=NR Vcco=3.30) uses 18 components (18 currently placed).
  (18 - Inputs, 0 - Outputs, 0 - Bidirectional)

Bank Summary
____________
If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' at
the end of a summary row. IOBs can be placed in a bank's Vref sites when none of
the IOBs in the bank require a Vref site.
NR - means Not Required

Bank 0 has 19 pads, 7 (36%) are utilized, with 7 possible dedicated Vref sites.
Vref should be set to NR volts.
     Name                 IO  Select Std     Vref   Vcco   Pad    Pin
     ----                 --  ----------     ------ ------ ------ ------
     idata<11>            I   LVTTL          NR     3.30   PAD2   P238   None   
     idata<10>            I   LVTTL          NR     3.30   PAD12  P237   None   
     idata<13>            I   LVTTL          NR     3.30   PAD13  P236   None   
Vref 
     idata<6>             I   LVTTL          NR     3.30   PAD23  P235   None   
     idata<9>             I   LVTTL          NR     3.30   PAD25  P231   None   
Vref 
     idata<12>            I   LVTTL          NR     3.30   PAD61  P222   None   
Vref 
     clk                  I   LVTTL          NR     3.30   GCLKPAD3 P213   None 
  

Bank 4 has 21 pads, 6 (28%) are utilized, with 7 possible dedicated Vref sites.
Vcco should be set to 2.50 volts.
     Name                 IO  Select Std     Vref   Vcco   Pad    Pin
     ----                 --  ----------     ------ ------ ------ ------
     db_x                 O   LVDS                  2.50   PAD385 P118   None   
     db                   O   LVDS                  2.50   PAD386 P117   None   
     ck_x                 O   LVDS                  2.50   PAD407 P114   None   
     ck                   O   LVDS                  2.50   PAD408 P113   None   
     da_x                 O   LVDS                  2.50   PAD409 P111   None   
Vref 
     da                   O   LVDS                  2.50   PAD410 P110   None   

Bank 5 has 20 pads, 3 (15%) are utilized, with 7 possible dedicated Vref sites.
Vref should be set to NR volts.
     Name                 IO  Select Std     Vref   Vcco   Pad    Pin
     ----                 --  ----------     ------ ------ ------ ------
     clk4x                I   LVTTL          NR     3.30   GCLKPAD1 P89    None 
  
     idata<0>             I   LVTTL          NR     3.30   PAD481 P87    None   
     idata<1>             I   LVTTL          NR     3.30   PAD540 P72    None   
Vref 

Bank 6 has 20 pads, 8 (40%) are utilized, with 7 possible dedicated Vref sites.
Vref should be set to NR volts.
     Name                 IO  Select Std     Vref   Vcco   Pad    Pin
     ----                 --  ----------     ------ ------ ------ ------
     idata<2>             I   LVTTL          NR     3.30   PAD599 P53    None   
     idata<3>             I   LVTTL          NR     3.30   PAD600 P52    None   
     idata<4>             I   LVTTL          NR     3.30   PAD601 P50    None   
Vref 
     idata<5>             I   LVTTL          NR     3.30   PAD602 P49    None   
     idata<7>             I   LVTTL          NR     3.30   PAD613 P48    None   
Vref 
     idata<15>            I   LVTTL          NR     3.30   PAD623 P47    None   
Vref 
     idata<8>             I   LVTTL          NR     3.30   PAD625 P42    None   
     idata<14>            I   LVTTL          NR     3.30   PAD637 P40    None   
Vref 

Placer completed in real time: 6 secs 

Dumping design to file tx2bit.ncd.

Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 3 secs 

0 connection(s) routed; 123 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 6 secs 
Starting iterative routing. 
Routing active signals.
...
End of iteration 1 
123 successful; 0 unrouted; (0) REAL time: 7 secs 
Constraints are met. 
Total REAL time: 7 secs 
Total CPU  time: 4 secs 
End of route.  123 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 4 secs 

Generating PAR statistics.
Dumping design to file tx2bit.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 9 secs 
Total CPU time to PAR completion: 5 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.
Tcl D:/Xilinx/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.

PAR completed successfully
Done: completed successfully.

Starting: 'exewrap @__parFloorPlannerAppExewrap.rsp'


Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Text-based Post-Place & Route Static Timing Report

Starting: 'exewrap @_ncdTOtwr_exewrap.rsp'


Creating TCL Process
Starting: 'trce -f __posttrc.rsp tx2bit.ncd -o tx2bit.twr tx2bit.pcf'


Release 4.2i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.



Loading design for application trce from file tx2bit.ncd.
   "tx2bit" is an NCD, version 2.37, device xcv1000e, package hq240, speed -6
Loading device for application trce from file 'v1000e.nph' in environment
D:/Xilinx.
--------------------------------------------------------------------------------
Release 4.2i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce -e 3 -l 3 -xml tx2bit tx2bit.ncd -o tx2bit.twr tx2bit.pcf

Design file:              tx2bit.ncd
Physical constraint file: tx2bit.pcf
Device,speed:             xcv1000e,-6 (PRELIMINARY 1.65 2001-12-19)
Report level:             error report
--------------------------------------------------------------------------------

WARNING:Timing:2491 - No timing constraints found, doing default enumeration.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 126 paths, 66 nets, and 123 connections (100.0% coverage)

Design statistics:
   Minimum period:   7.449ns (Maximum frequency: 134.246MHz)
   Maximum combinational path delay:  12.881ns
   Maximum net delay:   8.602ns


Analysis completed Sun Dec 15 14:49:29 2002
--------------------------------------------------------------------------------

Generating Report ...

Total time: 4 secs 
Tcl D:/Xilinx/data/projnav/_postRouteTiming.tcl detected that program 'trce -f __posttrc.rsp tx2bit.ncd -o tx2bit.twr tx2bit.pcf' completed successfully.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Post-Place & Route Static Timing Report

Launching: 'exewrap -tcl -command __launchTA.tcl'



ISE Auto-Make Log File
-----------------------

Updating: Post-Place & Route Static Timing Report

Launching: 'exewrap -tcl -command __launchTA.tcl'



ISE Auto-Make Log File
-----------------------