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You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_m_1> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_m_2> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux1_M0> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux1_M1> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux2_M0> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux2_M1> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux3_M0> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <piso4_mux3_M1> may hinder timing optimization. You may achieve better results by removing this property=========================================================================Final ResultsTop Level Output File Name : tx2bitOutput Format : NGCOptimization Criterion : SpeedTarget Technology : virtexeKeep Hierarchy : NoMacro Generator : macro+Design Statistics# IOs : 24Cell Usage :# BELS : 9# GND : 1# INV : 4# LUT1 : 3# VCC : 1# FlipFlops/Latches : 41# FD : 6# FD_1 : 7# FDC : 18# FDR : 2# FDR_1 : 1# LD : 3# LD_1 : 3# LDC_1 : 1# Clock Buffers : 2# BUFGP : 2# IO Buffers : 22# IBUF : 16# OBUF_LVDS : 6# Logical : 48# AND2 : 15# AND2b1 : 15# OR2 : 15# XOR2 : 3# Others : 18# FMAP : 18==================================================================================================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk4x | BUFGP | 32 |clk | BUFGP | 2 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 7.752ns (Maximum Frequency: 128.999MHz) Minimum input arrival time before clock: 4.818ns Maximum output required time after clock: 9.351ns Maximum combinational path delay: 4.493nsTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk4x'Delay: 3.876ns (Levels of Logic = 1) Source: ddrc_ddr_ld2 Destination: ddrc_ddr_ld1 Source Clock: clk4x rising Destination Clock: clk4x falling Data Path: ddrc_ddr_ld2 to ddrc_ddr_ld1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ LD_1:G->Q 2 1.091 1.072 ddrc_ddr_ld2 (ddrc_lrf) INV:I->O 1 0.468 0.920 ddrc_ddr_inv (ddrc_inv_lrf) LD:D 0.325 ddrc_ddr_ld1 ---------------------------------------- Total 3.876ns (1.884ns logic, 1.992ns route) (48.6% logic, 51.4% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk4x'Offset: 4.818ns (Levels of Logic = 3) Source: idata_5 Destination: piso2_FDC2 Destination Clock: clk4x rising Data Path: idata_5 to piso2_FDC2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.797 0.920 idata_5_IBUF (idata_5_IBUF) AND2:I1->O 1 0.468 0.920 piso2_mux3_U1 (piso2_mux3_M1) OR2:I0->O 1 0.468 0.920 piso2_mux3_U2 (piso2_m_2) FDC:D 0.325 piso2_FDC2 ---------------------------------------- Total 4.818ns (2.058ns logic, 2.760ns route) (42.7% logic, 57.3% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk4x'Offset: 9.351ns (Levels of Logic = 5) Source: ddrc_ddr_fd4 Destination: ck_x Source Clock: clk4x rising Data Path: ddrc_ddr_fd4 to ck_x Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD_1:C->Q 1 0.992 0.920 ddrc_ddr_fd4 (ddrc_crf) XOR2:I0->O 2 0.468 1.072 ddrc_ddr_xor (ddrc_qsel) AND2:I0->O 1 0.468 0.920 ddrc_ddr_m_U1 (ddrc_ddr_m_M1) OR2:I0->O 2 0.468 1.072 ddrc_ddr_m_U2 (c) LUT1:I0->O 1 0.468 0.920 I_INV_c (cn) OBUF_LVDS:I->O 1.583 data_cn (ck_x) ---------------------------------------- Total 9.351ns (4.447ns logic, 4.904ns route) (47.6% logic, 52.4% route)-------------------------------------------------------------------------Timing constraint: Default path analysisOffset: 4.493ns (Levels of Logic = 3) Source: idata_10 Destination: piso3_mux2_U3 Data Path: idata_10 to piso3_mux2_U3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.797 0.920 idata_10_IBUF (idata_10_IBUF) AND2:I1->O 1 0.468 0.920 piso3_mux2_U1 (piso3_mux2_M1) OR2:I0->O 1 0.468 0.920 piso3_mux2_U2 (piso3_m_1) FMAP:O 0.000 piso3_mux2_U3 ---------------------------------------- Total 4.493ns (1.733ns logic, 2.760ns route) (38.6% logic, 61.4% route)=========================================================================CPU : 6.70 / 6.97 s | Elapsed : 7.00 / 7.00 s --> EXEWRAP detected that program 'D:/Xilinx/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap @__ednTOngd_exewrap.rsp'
Starting: 'ngdbuild -f __ngdbuild.rsp 'Release 4.2i - ngdbuild E.35Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd e:/work/6_1pro/_ngo -nt timestamp -p xcv1000e-hq240-6tx2bit.ngc tx2bit.ngd Reading NGO file "E:/work/6_1pro/tx2bit.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "tx2bit.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "tx2bit.ngd" ...Writing NGDBUILD log file "tx2bit.bld"...NGDBUILD done.EXEWRAP detected that program 'ngdbuild' completed successfully.Done: completed successfully.
Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'
Creating TCL ProcessStarting: 'map -f _map.rsp'Release 4.2i - Map E.35Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Using target part "v1000ehq240-6".Removing unused or disabled logic...Running cover...Writing file tx2bit.ngm...Running directed packing...Running delay-based packing...Running related packing...Writing design file "tx2bit.ncd"...Design Summary: Number of errors: 0 Number of warnings: 0 Number of Slices: 37 out of 12,288 1% Number of Slices containing unrelated logic: 0 out of 37 0% Total Number Slice Registers: 40 out of 24,576 1% Number used as Flip Flops: 33 Number used as Latches: 7 Number of 4 input LUTs: 18 out of 24,576 1% Number of bonded IOBs: 22 out of 158 13% Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 407Additional JTAG gate count for IOBs: 1,152Mapping completed.See MAP report file "tx2bit.mrp" for details.Tcl D:/Xilinx/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap @__mapFloorPlannerAppExewrap.rsp'
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: View/Edit Placed Design (FloorPlanner)
Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'
Creating TCL ProcessStarting: 'map -f _map.rsp'Release 4.2i - Map E.35Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Using target part "v1000ehq240-6".Removing unused or disabled logic...Running cover...Writing file tx2bit.ngm...Running directed packing...Running delay-based packing...Running related packing...Writing design file "tx2bit.ncd"...Design Summary: Number of errors: 0 Number of warnings: 7 Number of Slices: 37 out of 12,288 1% Number of Slices containing unrelated logic: 0 out of 37 0% Total Number Slice Registers: 40 out of 24,576 1% Number used as Flip Flops: 33 Number used as Latches: 7 Number of 4 input LUTs: 18 out of 24,576 1% Number of bonded IOBs: 22 out of 158 13% Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 407Additional JTAG gate count for IOBs: 1,152Mapping completed.See MAP report file "tx2bit.mrp" for details.Tcl D:/Xilinx/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap @_nc1TOncd_exewrap.rsp'
Creating TCL ProcessFound _prepar.rspStarting: 'par -f _par.rsp'Release 4.2i - Par E.35Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".Constraints file: tx2bit.pcfLoading design for application par from file par_temp.ncd. "tx2bit" is an NCD, version 2.37, device xcv1000e, package hq240, speed -6Loading device for application par from file 'v1000e.nph' in environmentD:/Xilinx.Device speed data version: PRELIMINARY 1.65 2001-12-19.Resolving physical constraints.Finished resolving physical constraints.⌨️ 快捷键说明
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